Stacked semiconductor dies with selective capillary under fill
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a semiconductor device includes forming at least three stacks of semiconductor dies over a substrate, the stacks spaced apart from one another by gaps. A first sealing material such as a capillary under fill material is deposited into a first subset of the gaps. A second sealing material such as a mold resin is deposited into a second subset of the gaps. The first and second sealing materials are cured, and the die stacks are then singulated.
1. A semiconductor device comprising:
a first chip including a plurality of side surfaces;
a second chip including a plurality of side surfaces, the second chip being stacked with the first chip;
a first sealing material provided in direct contact with at least one of the plurality of side surfaces of the first chip and with at least one of the plurality of side surfaces of the second chip and filling a space between the first chip and the second chip; and
a second sealing material provided in direct contact with a remaining one or ones of the plurality of side surfaces of the first chip and with a remaining one or ones of the plurality of side surfaces of the second chip, the second sealing material being different from the first sealing material.
2. The semiconductor device according to claim 1 wherein the first sealing material has a first filler containing ratio and the second sealing material has a second filler containing ratio that is larger than the first filler containing ratio.
3. The semiconductor device according to claim 1 wherein the second sealing material does not occupy the space between the first chip and the second chip and is in contact with the first sealing material.
4. The semiconductor device according to claim 1 , further comprising an interface chip stacked with the first chip, and wherein each of the first and the second chips comprises a memory chip.
5. The semiconductor device according to claim 4 , further comprising a third sealing material provided in contact with each of the side surfaces of the interface chip and with the first and the second sealing materials.
6. A semiconductor device comprising:
a stack of a plurality of semiconductor dies, the stack having a plurality of side surfaces;
a first sealing material disposed directly on one of the side surfaces and extending between each two dies of the stack; and
a second sealing material disposed directly on another of the side surfaces, the second sealing material having a lower thermal cure shrinkage coefficient than the first sealing material.
7. The semiconductor device of claim 6 wherein the first sealing material has a lower filler containing ratio than the second sealing material.
8. The semiconductor device of claim 6 wherein the each two dies are stacked adjacently.
9. The semiconductor device of claim 6 wherein the stack of the plurality of semiconductor dies includes an interface chip and a memory chip.
10. The semiconductor device of claim 6 , wherein the first sealing material comprises a capillary under fill (CUF) material and the second sealing material comprises a mold resin material.