Vertical metal insulator metal capacitor
A semiconductor device and a method are disclosed herein. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.
1. A semiconductor device, comprising:
a device die;
a molding layer surrounding the device die;
a plurality of first vertical conductive structures formed within the molding layer;
a plurality of second vertical conductive structures formed within the molding layer;
a first polymer layer overlying the molding layer; and
a first redistribution layer overlying the first polymer layer to form a conductive plane, wherein the conductive plane is electrically coupled to the second vertical conductive structures, wherein the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.
2. The semiconductor device of claim 1 , wherein a molding compound is applied in the molding layer to surround the device die, and a dielectric material is applied in the molding layer to form the insulating structure.
3. The semiconductor device of claim 2 , wherein the dielectric material has a dielectric constant higher than that of the molding compound.
4. The semiconductor device of claim 2 , wherein the dielectric material comprises polyimide or polybenzoxazole.
5. The semiconductor device of claim 2 , wherein the dielectric material comprises silicon nitride or silicon dioxide.
6. The semiconductor device of claim 2 , wherein the dielectric material comprises ZrO 2 , Al 2 O 3 , HfOx, HfSiOx, ZrTiOx, TiO 2 , or TaOx.
7. The semiconductor device of claim 2 , wherein the dielectric material comprises a SrRuO 3 -SrTiO 3 -SrRuO 3 structure or a ZrO 2 -Al 2 O 3 -ZrO 2 structure.
8. The semiconductor device of claim 1 , wherein the first vertical conductive structures are distributed in a grid pattern, and the second vertical conductive structures are distributed in a grid pattern.
9. The semiconductor device of claim 1 , further comprising:
a second polymer layer overlying the first redistribution layer; and
a second redistribution layer overlying the second polymer layer;
wherein the device die and the conductive plane are electrically coupled via the second redistribution layer.
10. A semiconductor device, comprising:
a device die;
a molding layer surrounding the device die;
a plurality of first vertical conductive structures formed within the molding layer and electrically coupled to a first conductive plane;
a plurality of second vertical conductive structures formed within the molding layer and electrically coupled to a second conductive plane;
a first polymer layer overlying the molding layer; and
a first redistribution layer overlying the first polymer layer to form the second conductive plane, wherein an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.
11. The semiconductor device of claim 10 , wherein the second conductive plane is disposed over the molding layer.
12. The semiconductor device of claim 10 , wherein the insulating structure comprises a dielectric material.
13. The semiconductor device of claim 12 , wherein the dielectric material has a dielectric constant higher than that of a molding compound applied in the molding layer.
14. The semiconductor device of claim 10 , further comprising:
a second polymer layer overlying the first redistribution layer;
a second redistribution layer overlying the second polymer layer; and
a third polymer layer overlying the second redistribution layer.
15. A semiconductor device, comprising:
a device die;
a capacitor structure, comprising:
a plurality of first vertical conductive structures;
a plurality of second vertical conductive structures; and
an insulating structure between the first vertical conductive structures and the second vertical conductive structures;
a molding compound in a molding layer surrounding the capacitor structure and the device die;
a first polymer layer overlying the molding layer; and
a first redistribution layer overlying the first polymer layer to form a second conductive plane, wherein the second conductive plane is electrically coupled to the second vertical conductive structures.
16. The semiconductor device of claim 15 , wherein the insulating structure comprises a dielectric material.
17. The semiconductor device of claim 16 , wherein the dielectric material has a dielectric constant higher than that of the molding compound.
18. The semiconductor device of claim 15 , further comprising:
a backside redistribution layer overlying a substrate to form a first conductive plane;
wherein the first conductive plane is electrically coupled to the first vertical conductive structures.
19. The semiconductor device of claim 18 , wherein the backside redistribution layer is embedded in the molding layer.
20. The semiconductor device of claim 10 , further comprising:
a backside redistribution layer underlying the molding layer to form the first conductive plane.