IP Library Granted Patent US 9,947,612
Granted Patent B2
US 9,947,612 · App. 14/957,785 · Granted Apr 17, 2018

Semiconductor device with frame having arms and related methods

Inventors: Jefferson Talledo (Calamba, PH); Rammil Seguido (Malolos, PH)
Assignee: STMICROELECTRONICS, INC.
H01L23/49531H01L21/563H01L23/49503H01L23/49541H01L23/49548H01L23/49568H01L23/49575H01L23/49861H01L24/49H01L24/85H01L21/561H01L23/3107H01L2224/45124H01L2224/45139H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/4918H01L2224/73265H01L2224/92247H01L2224/97H01L2924/181
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Quick Facts
Patent No.
US 9,947,612
App. No.
14/957,785
Granted
Apr 17, 2018
Kind
B2
Abstract

A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.

Claims (46)

1. A semiconductor device comprising:

a circuit board having an opening therein, and first and second opposing major surfaces;

a frame comprising an integrated circuit (IC) die pad in the opening, and a plurality of arms extending outwardly from said IC die pad, each arm devoid of a contact pad and extending diagonally outward from a respective corner of the IC die pad, each arm having

a distal end coupled to the first major surface of said circuit board, and

a proximal end extending over the first major surface of said circuit board and being spaced apart from the first major surface of said circuit board;

at least one IC mounted on said IC die pad;

a plurality of bond wires coupling said circuit board with said at least one IC; and

encapsulation material surrounding said at least one IC, said plurality of bond wires, and said plurality of arms;

said encapsulation material being between the proximal ends of said plurality of arms and the first major surface of said circuit board.

2. The semiconductor device of claim 1 wherein said IC die pad has first and second opposing surfaces, the first opposing surface being adjacent said at least one IC, the second opposing surface being exposed through the opening of said circuit board.

3. The semiconductor device of claim 1 wherein said IC die pad is rectangle-shaped.

4. The semiconductor device of claim 1 wherein said IC die pad has a bottom surface aligned with the second major surface of said circuit board.

5. The semiconductor device of claim 1 wherein said circuit board comprises a dielectric layer, and a plurality of electrically conductive traces carried by said dielectric layer and respectively coupled to said plurality of bond wires.

6. The semiconductor device of claim 1 wherein said at least one IC comprises a substrate, and a plurality of bond pads carried by said substrate and respectively coupled to said plurality of bond wires.

7. The semiconductor device of claim 1 further comprising an adhesive layer between respective distal ends of said plurality of arms and said circuit board.

8. The semiconductor device of claim 1 further comprising an adhesive layer between said at least one IC and said IC die pad.

9. The semiconductor device of claim 1 wherein said frame comprises a metallic material.

10. The semiconductor device of claim 1 wherein said encapsulation material surrounds peripheral edges of said circuit board and said frame.

11. A semiconductor device comprising

a circuit board having an opening therein, and first and second opposing major surfaces;

a frame comprising a rectangle-shaped integrated circuit (IC) die pad in the opening, and a plurality of arms free from an overlying contact pad, each arm extending diagonally outwardly from a respective corner of said rectangle-shaped IC die pad, each arm having

a distal end coupled to the first major surface of said circuit board, and

a proximal end extending over the first major surface of said circuit board and being spaced apart from the first major surface of said circuit board;

at least one IC mounted on said rectangle-shaped IC die pad;

said rectangle-shaped IC die pad having first and second opposing surfaces, the first opposing surface being adjacent said at least one IC, the second opposing surface being exposed through the opening of said circuit board;

a plurality of bond wires coupling said circuit board with said at least one IC; and

encapsulation material surrounding said at least one IC, said plurality of bond wires, and said plurality of arms;

said encapsulation material being between the proximal ends of said plurality of arms and the first major surface of said circuit board.

12. The semiconductor device of claim 11 wherein the second opposing surface of said rectangle-shaped IC die pad is aligned with the second major surface of said circuit board.

13. The semiconductor device of claim 11 wherein said circuit board comprises a dielectric layer, and a plurality of electrically conductive traces carried by said dielectric layer and respectively coupled to said plurality of bond wires.

14. The semiconductor device of claim 11 wherein said at least one IC comprises a substrate, and a plurality of bond pads carried by said substrate and respectively coupled to said plurality of bond wires.

15. The semiconductor device of claim 11 further comprising an adhesive layer between respective distal ends of said plurality of arms and said circuit board.

16. A semiconductor device comprising:

a circuit board having an opening therein, and first and second opposing major surfaces;

a frame devoid of an electrical connection to an element external to the frame and comprising an integrated circuit (IC) die pad in the opening, and a plurality of arms extending outwardly from said IC die pad, each arm extending diagonally outwardly from a respective corner of the IC die pad, each arm having

a distal end coupled to the first major surface of said circuit board and being aligned with an outer lateral edge of said circuit board, and

a proximal end extending over the first major surface of said circuit board and being spaced apart from the first major surface of said circuit board;

at least one IC mounted on said IC die pad;

a plurality of bond wires coupling said circuit board with said at least one IC;

encapsulation material surrounding said at least one IC, said plurality of bond wires, and said plurality of arms;

said encapsulation material being between the proximal ends of said plurality of arms and the first major surface of said circuit board; and

an adhesive layer between respective distal ends of said plurality of arms and said circuit board.

17. The semiconductor device of claim 16 wherein said IC die pad has first and second opposing surfaces, the first opposing surface being adjacent said at least one IC, the second opposing surface being exposed through the opening of said circuit board.

18. The semiconductor device of claim 16 wherein said IC die pad is rectangle-shaped; and wherein each arm extends diagonally outward from a respective corner of said rectangle-shaped IC die pad.

19. The semiconductor device of claim 16 wherein said IC die pad has a bottom surface aligned with the second major surface of said circuit board.

20. The semiconductor device of claim 16 wherein said circuit board comprises a dielectric layer, and a plurality of electrically conductive traces carried by said dielectric layer and respectively coupled to said plurality of bond wires.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2024
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 068025/0112 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: TALLEDO, JEFFERSON; SEGUIDO, RAMMIL
To: STMICROELECTRONICS, INC.
Reel/Frame 037229/0144 →
Continuity (1)
Related Publication 20170162479A1 · Jun 8, 2017