IP Library Granted Patent US 9,947,803
Granted Patent B2
US 9,947,803 · App. 13/097,572 · Granted Apr 17, 2018

Amorphous oxide and thin film transistor

Inventors: Hideo Hosono (Kanagawa, JP); Masahiro Hirano (Tokyo, JP); Hiromichi Ota (Aichi, JP); Toshio Kamiya (Kanagawa, JP); Kenji Nomura (Tokyo, JP)
Assignees: JAPAN SCIENCE AND TECHNOLOGY AGENCY; CANON KABUSHIKI KAISHA; TOKYO INSTITUTE OF TECH
H01L29/78696C23C14/0021C23C14/086C23C14/28C23C14/3414H01L21/02554H01L21/02565H01L21/02631H01L27/1225H01L29/7869H01L29/78693
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Quick Facts
Patent No.
US 9,947,803
App. No.
13/097,572
Granted
Apr 17, 2018
Kind
B2
Abstract

The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 10 18 /cm 3 , and a thin film transistor using such an amorphous oxide. In a thin film transistor having a source electrode 6 , a drain electrode 5 , a gate electrode 4 , a gate insulating film 3 , and a channel layer 2 , an amorphous oxide having an electron carrier concentration less than 10 18 /cm 3 is used in the channel layer 2.

Claims (11)

1. A method of forming a field effect thin film transistor device which is used as a normally-OFF type, comprising:

providing a drain electrode;

providing a source electrode;

sputter depositing a channel layer which is contacting with the drain electrode and the source electrode, the channel layer being comprised of a transparent and amorphous indium-gallium-zinc oxide film,

wherein the sputtering deposition is performed in an oxygen-partial-pressure-controlled atmosphere at room temperature without adding impurity ions to the channel layer to increase electrical resistance, and using a polycrystalline sinter represented by InGaO 3 (ZnO) m (wherein m is a natural number less than 6) as a target material,

whereby forming the channel layer in which an atomic ratio In:Ga:Zn is 1:1:m (wherein m is a natural number less than 6) having an electron carrier concentration less than 10 16 /cm 3 determined by Hall-effect measurement and an electron mobility of 1 cm 2 /(V·sec) or more at room temperature;

providing a gate electrode; and

providing a gate insulating film positioned between the gate electrode and the channel.

2. The method of forming a field effect thin film transistor according to claim 1 , wherein the substrate is one of a glass plate, a plastic plate or a plastic film.

3. The method of forming a field effect thin film transistor according to claim 1 , further comprising a step of heating the indium-gallium-zinc oxide film in a reducing atmosphere to increase the electron carrier concentration after the film formation.

4. The method of forming a field effect thin film transistor according to claim 1 , the transistor is a switching element of LCDs or organic EL displays.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2013
From: JAPAN SCIENCE AND TECHNOLOGY AGENCY
To: JAPAN SCIENCE AND TECHNOLOGY AGENCY; CANON KABUSHIKI KAISHA; TOKYO INSTITUTE OF TECHNOLOGY
Reel/Frame 030728/0079 →
Priority Claims (2)
JP 2004-071477 · Mar 12, 2004 · national
JP 2004-325938 · Nov 10, 2004 · national
Continuity (3)
Continuation 12504158 · Jul 16, 2009
Division 10592431
Related Publication 20110201162A1 · Aug 18, 2011