Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.
1. A method of forming a semiconductor structure comprising:
forming at least one nanowire segment wrapped around by a gate structure located on a substrate, the at least one nanowire segment having a first end and a second end opposite the first end;
forming a first epitaxial semiconductor region extending from the first end of the at least one nanowire segment, the first epitaxial semiconductor region comprising a first semiconductor material and dopants of a first conductivity type; and
forming a second epitaxial semiconductor region extending from the second end of the at least one nanowire segment, the second epitaxial semiconductor region comprising a second semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.
2. The method of claim 1 , wherein the at least one nanowire segment comprises the second semiconductor material and is intrinsic.
3. The method of claim 1 , wherein at least one nanowire segment comprises intrinsic silicon, the first epitaxial semiconductor region comprises p-doped germanium, and the second epitaxial semiconductor region composes n-doped silicon.
4. The method of claim 1 , wherein the forming the at least one nanowire segment comprises:
forming at least one nanowire suspended by a first pad portion and a second pad portion over the substrate;
forming the gate structure around a portion of the at least one nanowire; and
removing portions of the at least one nanowire that is not covered by the gate structure, wherein the portion of the at least one nanowire that remains covered by the gate structure provides the nanowire segment.
5. The method of claim 4 , wherein the substrate includes a handle substrate and a buried insulator layer present over the handle substrate, wherein the at least one nanowire is suspended above a recessed region of the buried insulator layer.
6. The method of claim 5 , wherein the forming the at least one nanowire comprising:
providing a semiconductor insulator substrate (SOI) comprising, from bottom to top, the handle substrate, the buried insulator layer and a top semiconductor layer;
patterning the top semiconductor layer to provide a top semiconductor portion comprising the first pad portion, the second pad portion and at least one nanowire portion connecting the first pad portion and the second pad portion; and
converting the at least one nanowire portion to the at least one nanowire by annealing.
7. The method of claim 5 , wherein the recess portion of the buried insulator layer is formed by isotropic etch.
8. The method of claim 5 , wherein the gate structure comprises a first portion located above a top surface of the at least one nanowire segment and a second portion located within a space between the at least one nanowire segment and the recessed region of the buried insulator layer.
9. The method of claim 5 , wherein forming the gate structure comprises:
forming a gate dielectric layer over exposed surfaces of the at least one nanowire, the first pad portion, the second pad portion and the recessed region of the buried insulator layer;
forming a gate electrode layer over the gate dielectric layer, the gate electrode layer filling the space between the at least one nanowire and the recessed region of the buried insulator layer;
patterning the gate dielectric layer and the gate electrode layer to provide a gate stack wrapping around the portion of the at least one nanowire; and
forming a gate spacer on sidewalls of the gate stack.
10. The method of claim 1 , wherein the first end of the at least one nanowire segment is vertically aligned with a first sidewall of the gate structure, and a second end of the at least one nanowire segment is vertically aligned with a second sidewall of the gate structure opposite the first sidewall.
11. The method of claim 1 , wherein the forming the first epitaxial semiconductor region comprises:
forming a patterned first mask layer covering the second end of the at least one nanowire segment and the gate structure, while exposing the first end of the at least one nanowire segment;
epitaxially growing a doped first semiconductor material from the exposed first end of the at least one nanowire segment to provide the first epitaxial semiconductor region; and
removing the patterned first mask layer.
12. The method of claim 10 , wherein the forming the second epitaxial semiconductor region comprises:
forming a patterned second mask layer covering the first epitaxial semiconductor region, while exposing the second end of the at least one nanowire segment;
epitaxially growing a doped second semiconductor material from the exposed second end of the at least one nanowire segment to provide the second epitaxial semiconductor region; and
removing the patterned second mask layer.
13. The method of claim 1 , further comprising forming a first metal semiconductor alloy region atop the first epitaxial semiconductor region, and a second metal semiconductor alloy region atop the second epitaxial semiconductor region.
14. The method of claim 13 , wherein the forming the first metal semiconductor alloy region and the second metal semiconductor alloy region comprises:
forming a metal layer on the exposed surfaces of the first epitaxial semiconductor region and the second epitaxial semiconductor region;
forming the first metal semiconductor alloy region and the second metal semiconductor alloy region by annealing; and
removing an unreacted portion of the metal layer.
15. The method of claim 14 , wherein each of the first metal semiconductor alloy region and the second metal semiconductor alloy region comprises a silicide or a germicide.
16. The method of claim 13 , further comprising forming a contact level dielectric layer over the substrate, the gate structure, the first epitaxial semiconductor region and the second epitaxial semiconductor region.
17. The method of claim 16 , further comprising planarizing the contact level dielectric layer, wherein a planarized top surface of the contact level dielectric layer is located above a topmost surface of the gate structure.
18. The method of claim 16 , further comprising forming a first contact structure contacting a top surface of the first metal semiconductor alloy region, and a second contact structure contacting a top surface of the second metal semiconductor alloy region.
19. The method of claim 18 , wherein the forming the first contact structure and the second contact structure comprises:
forming a first contacting opening extending through the contact level dielectric layer to expose the top surface of the first metal semiconductor alloy region and a second contacting opening extending through the contact level dielectric layer to expose the top surface of the second metal semiconductor alloy region; and
filling the first contact opening and the second contact opening with a conductive material.
20. The method of claim 19 , further comprising forming a contact liner on sidewalls and a bottom surface of each of the first contact opening and the second contact opening prior to the filling the first contact opening and the second contact opening with the conductive material.