Photodiode and photodiode array
A p − type semiconductor substrate 20 has a first principal surface 20 a and a second principal surface 20 b opposed to each other and includes a photosensitive region 21 . The photosensitive region 21 is composed of an n + type impurity region 23 , a p + type impurity region 25 , and a region to be depleted with application of a bias voltage in the p − type semiconductor substrate 20 . An irregular asperity 10 is formed in the second principal surface 20 b of the p − type semiconductor substrate 20 . An accumulation layer 37 is formed on the second principal surface 20 b side of the p − type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.
1. A photodiode array comprising:
a silicon substrate comprised of a semiconductor of a first conductivity type and having a first principal surface and a second principal surface opposed to each other,
wherein a plurality of avalanche photodiodes each composed of a pn junction between a semiconductor region of the first conductivity type having a higher impurity concentration than the silicon substrate and a semiconductor region of a second conductivity type are arranged on the first principal surface side of the silicon substrate,
wherein on the second principal surface side of the silicon substrate, an accumulation layer of the first conductivity type having a higher impurity concentration than the silicon substrate is formed and an irregular asperity is formed in at least regions opposed to the avalanche photodiodes,
wherein the regions opposed to the avalanche photodiodes in the second principal surface of the silicon substrate are optically exposed, and
wherein the second principal surface where the irregular asperity is formed in at least the regions opposed to the avalanche photodiodes constitutes a light incident surface, light incident from the second principal surface travels in the silicon substrate, the photodiode being a back-illuminated type.
2. The photodiode array according to claim 1 , wherein in the silicon substrate, a portion where the plurality of avalanche photodiodes are arranged is thinned from the second principal surface side while leaving a surrounding region around said thinned portion.
3. The photodiode array according to claim 1 , wherein a thickness of the accumulation layer of the first conductivity type is larger than a height difference of the irregular asperity.
4. The photodiode array according to claim 1 , wherein the light incident from the second principal surface and traveling in the silicon substrate is reflected, scattered, or diffused by the irregular asperity.
5. The photodiode array according to claim 1 , wherein the irregular asperity is formed by applying pulsed laser beam.