IP Library › Granted Patent US 10,007,160
Granted Patent B2
US 10,007,160 · App. 15/711,029 · Granted Jun 26, 2018

Display device

Inventors: Hajime Kimura (Atsugi, JP); Atsushi Umezaki (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G02F1/1368G02F1/13624G02F1/136259G02F1/136286G09G3/006G09G3/3648H01L27/124H01L27/1225H01L27/1255H01L29/7869G02F1/1339G02F1/13439G02F1/133345G02F1/134309G02F1/167G02F2001/133302G02F2001/136254G09G2230/00G09G2310/0251H01L29/42384
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Quick Facts
Patent No.
US 10,007,160
App. No.
15/711,029
Granted
Jun 26, 2018
Kind
B2
Abstract

An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current. A precharge circuit or an inspection circuit is formed in addition to a pixel circuit. The off-state current is low because the oxide semiconductor is used. Thus, it is not likely that a signal or voltage is leaked in the precharge circuit or the inspection circuit to cause defective display. As a result, a display device that performs accurate display can be provided.

Claims (36)

1. A liquid crystal display device comprising:

a pixel portion including a first pixel and a second pixel each performing red display; and

a circuit configured to inspect the pixel portion, the circuit including a third transistor and a fourth transistor,

wherein the first pixel includes a first transistor and a first liquid crystal element,

wherein the second pixel includes a second transistor and a second liquid crystal element,

wherein one of source and drain of the first transistor is electrically connected to a first signal line and the other of source and drain of the first transistor is electrically connected to the first liquid crystal element,

wherein one of source and drain of the second transistor is electrically connected to a second signal line and the other of source and drain of the second transistor is electrically connected to the second liquid crystal element,

wherein gates of the third transistor and the fourth transistor are electrically connected to each other,

wherein one of source and drain of the third transistor is electrically connected to the first signal line,

wherein one of source and drain of the fourth transistor is electrically connected to the second signal line,

wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes an oxide semiconductor layer, an oxide insulating layer over and in contact with the oxide semiconductor layer, and a silicon nitride film over and in contact with the oxide insulating layer.

2. The liquid crystal display device according to claim 1 ,

wherein the other of source and drain of the third transistor and the other of source and drain of the fourth transistor are electrically connected to different wirings.

3. The liquid crystal display device according to claim 1 ,

wherein an off-state current per channel width of 1 μm of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is 1 zA/μm.

4. The liquid crystal display device according to claim 1 ,

wherein carrier density of the oxide semiconductor layer is less than 1×10 12 /cm 3 .

5. An electronic device including the liquid crystal display device according to claim 1 and an operation switch.

6. A liquid crystal display device comprising:

a pixel portion including a first pixel and a second pixel each performing red display; and

a circuit configured to inspect the pixel portion, the circuit including a third transistor and a fourth transistor,

wherein the first pixel includes a first transistor and a first liquid crystal element,

wherein the second pixel includes a second transistor and a second liquid crystal element,

wherein one of source and drain of the first transistor is electrically connected to a first signal line and the other of source and drain of the first transistor is electrically connected to the first liquid crystal element,

wherein one of source and drain of the second transistor is electrically connected to a second signal line and the other of source and drain of the second transistor is electrically connected to the second liquid crystal element,

wherein gates of the third transistor and the fourth transistor are electrically connected to each other,

wherein one of source and drain of the third transistor is electrically connected to the first signal line,

wherein one of source and drain of the fourth transistor is electrically connected to the second signal line,

wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes an oxide semiconductor layer, a silicon oxide film over and in contact with the oxide semiconductor layer, and a silicon nitride film over and in contact with the silicon oxide film.

7. The liquid crystal display device according to claim 6 ,

wherein the other of source and drain of the third transistor and the other of source and drain of the fourth transistor are electrically connected to different wirings.

8. The liquid crystal display device according to claim 6 ,

wherein an off-state current per channel width of 1 μm of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is 1 zA/μm.

9. The liquid crystal display device according to claim 6 ,

wherein carrier density of the oxide semiconductor layer is less than 1×10 12 /cm 3 .

10. An electronic device including the liquid crystal display device according to claim 6 and an operation switch.

Priority Claims (1)
JP 2010-028285 · Feb 11, 2010 · national
Continuity (4)
Division 15262611 · Sep 12, 2016
Continuation 14602876 · Jan 22, 2015
Continuation 13021955 · Feb 7, 2011
Related Publication 20180017819A1 · Jan 18, 2018
Cited By (1)
US 12,416,838