IP Library › Granted Patent US 10,008,591
Granted Patent B2
US 10,008,591 · App. 15/683,860 · Granted Jun 26, 2018

Semiconductor device, fabrication method for semiconductor device, power supply apparatus and high-frequency amplifier

Inventors: Masato Nishimori (Atsugi, JP); Tatsuya Hirose (Yokohama, JP); Atsushi Yamada (Isehara, JP)
Assignee: FUJITSU LIMITED
H01L29/7787H01L21/3245H01L21/764H01L29/0649H01L29/0657H01L29/1075H01L29/41766H01L29/66462H01L29/7786H01L23/3171H01L29/2003H01L29/207H01L29/41758H01L2224/0603H01L2224/48247H01L2224/48257H01L2224/4903
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,008,591
App. No.
15/683,860
Granted
Jun 26, 2018
Kind
B2
Abstract

A semiconductor device is configured including a p-type back barrier layer provided over a substrate and formed from a p-type nitride semiconductor in which Mg or Zn is doped, a nitride semiconductor stacked structure provided over the p-type back barrier layer, the nitride semiconductor stacked structure including an electron transit layer and an electron supply layer, a source electrode, a drain electrode and a gate electrode provided over the nitride semiconductor stacked structure, and a groove extending to the p-type back barrier layer.

Claims (13)

1. A fabrication method for a semiconductor device, comprising:

forming a p-type back barrier layer from a p-type nitride semiconductor in which Mg or Zn is doped over a substrate;

forming a nitride semiconductor stacked structure including an electron transit layer and an electron supply layer over the p-type back barrier layer;

forming a source electrode, a drain electrode and a gate electrode over the nitride semiconductor stacked structure;

forming a groove extending to the p-type back barrier layer; and

performing an anneal process for desorbing hydrogen from the p-type back barrier layer through the groove to activate the p-type back barrier layer.

2. The fabrication method for a semiconductor device according to claim 1 , further comprising providing a hydrogen occlusion alloy in the groove before the anneal process is performed after the groove is formed; wherein

in the performing the anneal process, hydrogen is desorbed from the p-type back barrier layer using the groove and the hydrogen occlusion alloy formed in the groove to activate the hydrogen occlusion alloy.

3. The fabrication method for a semiconductor device according to claim 2 , wherein the hydrogen occlusion alloy contains any one of Ti, Zr, Pd and Mg.

4. The fabrication method for a semiconductor device according to claim 1 , wherein, in the forming the groove, the groove is formed so as to extend from the surface of the nitride semiconductor stacked structure to the p-type back barrier layer.

5. The fabrication method for a semiconductor device according to claim 1 , wherein, in the forming the groove, the groove is formed in an active region or in the proximity of the active region.

6. The fabrication method for a semiconductor device according to claim 1 , wherein, in the forming the source electrode, drain electrode and gate electrode, the source electrode or the drain electrode is formed over the groove.

7. The fabrication method for a semiconductor device according to claim 1 , wherein, in the forming the groove, the groove is formed so as to extend from the back face of the substrate to the p-type back barrier layer.

Priority Claims (1)
JP 2015-043667 · Mar 5, 2015 · national
Continuity (2)
Division 15043720 · Feb 15, 2016
Related Publication 20170352755A1 · Dec 7, 2017
Cited By (1)
US 12,446,252