IP Library › Granted Patent US 10,032,492
Granted Patent B2
US 10,032,492 · App. 15/455,226 · Granted Jul 24, 2018

Semiconductor device, driver IC, computer and electronic device

Inventor: Tatsuya Onuki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C7/065G11C8/10G11C11/4097G11C11/4087G11C11/4091
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,032,492
App. No.
15/455,226
Granted
Jul 24, 2018
Kind
B2
Abstract

A semiconductor device that is novel, is capable of high-speed operation, consumes low power, or occupies a small area is provided. The semiconductor device includes a memory portion, a control circuit, and a plurality of wirings. The memory portion includes a plurality of memory circuits. The memory circuit includes a memory cell. The memory cell is electrically connected to a wiring. A first signal that indicates the amount of data that are written to or read from the memory portion is supplied to the control circuit. The control circuit has the function of controlling the number of the wirings to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal.

Claims (85)

1. A semiconductor device comprising:

a memory portion; and

a control circuit,

wherein the memory portion comprises a plurality of memory circuits,

wherein each of the plurality of memory circuits comprises a memory cell and a wiring,

wherein the memory cell is electrically connected to the wiring,

wherein the control circuit is supplied with a first signal that indicates the amount of data to be written to the memory portion or the amount of data to be read from the memory portion, and

wherein the control circuit is configured to control the number of the plurality of memory circuits to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal.

2. The semiconductor device according to claim 1 ,

wherein the control circuit is supplied with an address signal, and

wherein the second signal is generated on the basis of the first signal and the address signal.

3. A driver IC comprising:

a frame memory comprising the semiconductor device according to claim 1 ;

a controller; and

a source driver.

4. A computer comprising:

the semiconductor device according to claim 1 ;

an input device;

an output device; and

a CPU.

5. An electronic device comprising:

the semiconductor device according to claim 1 ; and

at least one of a display portion, a microphone, a speaker, and a control key.

6. A semiconductor device comprising:

a memory portion; and

a control circuit,

wherein the memory portion comprises a plurality of memory circuits,

wherein each of the plurality of memory circuits comprises a memory cell, a first wiring, a second wiring and an amplifier circuit,

wherein the memory cell is electrically connected to the first wiring and the second wiring,

wherein the amplifier circuit is electrically connected to the second wiring,

wherein the control circuit is supplied with a first signal that indicates the amount of data to be written to the memory portion or the amount of data to be read from the memory portion,

wherein the control circuit is configured to control the number of the plurality of memory circuits to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal, and

wherein the control circuit is configured to control the number of the plurality of memory circuits to which a third signal for operating the amplifier circuit is simultaneously supplied on the basis of the first signal.

7. The semiconductor device according to claim 6 ,

wherein the amplifier circuit is configured to temporarily retain data that have been read from the memory cell.

8. The semiconductor device according to claim 6 ,

wherein the memory cell comprises a transistor,

wherein the transistor comprises an oxide semiconductor in a channel formation region, and

wherein the memory cell is stacked over the amplifier circuit.

9. The semiconductor device according to claim 6 ,

wherein the control circuit is supplied with an address signal, and

wherein the second signal is generated on the basis of the first signal and the address signal.

10. A driver IC comprising:

a frame memory comprising the semiconductor device according to claim 6 ;

a controller; and

a source driver.

11. A computer comprising:

the semiconductor device according to claim 6 ;

an input device;

an output device; and

a CPU.

12. An electronic device comprising:

the semiconductor device according to claim 6 ; and

at least one of a display portion, a microphone, a speaker, and a control key.

13. A semiconductor device comprising:

a memory portion; and

a control circuit,

wherein the memory portion comprises a plurality of memory circuits,

wherein each of the plurality of memory circuits comprises a memory cell, a first wiring, a second wiring and an amplifier circuit,

wherein the memory cell is electrically connected to the first wiring and the second wiring,

wherein the amplifier circuit is electrically connected to the second wiring,

wherein the control circuit is supplied with a first signal that indicates the number of the plurality of memory circuits to be selected,

wherein the control circuit is configured to control the number of the plurality of memory circuits to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal, and

wherein the control circuit is configured to control the number of the plurality of memory circuits to which a third signal for operating the amplifier circuit is simultaneously supplied on the basis of the first signal.

14. The semiconductor device according to claim 13 ,

wherein the amplifier circuit is configured to temporarily retain data that have been read from the memory cell.

15. The semiconductor device according to claim 13 ,

wherein the memory cell comprises a transistor,

wherein the transistor comprises an oxide semiconductor in a channel formation region, and

wherein the memory cell is stacked over the amplifier circuit.

16. The semiconductor device according to claim 13 ,

wherein the control circuit is supplied with an address signal, and

wherein the second signal is generated on the basis of the first signal and the address signal.

17. A driver IC comprising:

a frame memory comprising the semiconductor device according to claim 13 ;

a controller; and

a source driver.

18. A computer comprising:

the semiconductor device according to claim 13 ;

an input device;

an output device; and

a CPU.

19. An electronic device comprising:

the semiconductor device according to claim 13 ; and

at least one of a display portion, a microphone, a speaker, and a control key.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2017
From: ONUKI, TATSUYA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 041602/0250 →
Priority Claims (2)
JP 2016-055307 · Mar 18, 2016 · national
JP 2016-062369 · Mar 25, 2016 · national
Continuity (1)
Related Publication 20170270977A1 · Sep 21, 2017
Cited By (2)
US 12,260,898 US 12,289,878