IP Library › Granted Patent US 12,289,878
Granted Patent B2
US 12,289,878 · App. 17/623,299 · Granted Apr 29, 2025

Semiconductor device and method of manufacturing semiconductor device

Inventors: Tatsuya Onuki (Atsugi, JP); Takanori Matsuzaki (Atsugi, JP); Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10B12/00H01L27/1225H01L27/1255H01L29/66969H01L29/78648H01L29/7869H10B12/05H10B12/30H01L21/8258H01L27/0688H01L27/1207H10B12/033H10B12/315
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Quick Facts
Patent No.
US 12,289,878
App. No.
17/623,299
Granted
Apr 29, 2025
Kind
B2
Abstract

A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

Claims (44)

1. A semiconductor device comprising:

a first conductor positioned over a substrate;

an oxide positioned in direct contact with a top surface of the first conductor;

a second conductor, a third conductor, and a fourth conductor positioned over the oxide;

a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor;

a second insulator positioned in the first opening;

a fifth conductor positioned over the second insulator;

a third insulator positioned in the second opening; and

a sixth conductor positioned over the third insulator; insulator,

wherein the third conductor is positioned to overlap with the first conductor,

wherein the first opening is formed to overlap with a region between the second conductor and the third conductor, and

wherein the second opening is formed to overlap with a region between the third conductor and the fourth conductor.

2. The semiconductor device according to claim 1 ,

further comprising a first capacitor and a second capacitor,

wherein the first capacitor is electrically connected to the second conductor, and

wherein the second capacitor is electrically connected to the fourth conductor.

3. The semiconductor device according to claim 2 ,

wherein the first capacitor is positioned over the second conductor, and

wherein the second capacitor is positioned over the fourth conductor.

4. The semiconductor device according to claim 1 ,

wherein the first conductor is connected to a wiring provided below the first conductor.

5. The semiconductor device according to claim 1 ,

wherein the second insulator is in contact with a top surface of the oxide and a side surface of the first insulator, and

wherein the third insulator is in contact with the top surface of the oxide and the side surface of the first insulator.

6. The semiconductor device according to claim 1 ,

wherein the oxide comprises a first oxide and a second oxide over the first oxide,

wherein the first oxide and the second oxide each comprise indium, an element M (M is one or more selected from gallium, aluminum, yttrium, and tin), and zinc, and

wherein an atomic ratio of indium to the element M in the first oxide is lower than an atomic ratio of indium to the element M in the second oxide.

7. A method of manufacturing a semiconductor device, comprising the steps of:

forming a first conductor over a substrate;

depositing an oxide film in direct contact with a top surface of the first conductor;

depositing a first conductive film over the oxide film;

forming an oxide and a second conductor by processing the oxide film and the first conductive film into an island shape;

forming a first insulator covering the oxide and the second conductor;

removing parts of the first insulator to form a first opening and a second opening each overlapping with the second conductor;

removing parts of the second conductor that overlap with the first opening and the second opening to form a third conductor, a fourth conductor, and a fifth conductor, the fourth conductor being positioned to overlap with the first conductor;

exposing regions of the oxide that do not overlap with the third conductor, the fourth conductor, and the fifth conductor;

depositing a first insulating film in contact with a top surface of the oxide;

performing microwave treatment in an atmosphere comprising oxygen;

depositing a second conductive film over the first insulating film; and

forming a second insulator and a sixth conductor in the first opening and forming a third insulator and a seventh conductor in the second opening by performing a polishing treatment on the first insulating film and the second conductive film until a top surface of the first insulator is exposed.

8. The semiconductor device according to claim 1 ,

wherein the second insulator is in contact with a top surface of the oxide and an inner surface of the first opening, and

wherein the third insulator is in contact with the top surface of the oxide and an inner surface of the second opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2021
From: ONUKI, TATSUYA; MATSUZAKI, TAKANORI; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 058487/0611 →
Priority Claims (1)
JP 2019-129905 · Jul 12, 2019 · national
Continuity (1)
Related Publication 20220328486A1 · Oct 13, 2022
References Cited (35)
US 9773919B2 · Sasagawa et al. · 2017 [cited by applicant]
US 9935203B2 · Sasagawa et al. · 2018 [cited by applicant]
US 9978774B2 · Yamazaki et al. · 2018 [cited by applicant]
US 10032492B2 · Onuki · 2018 [cited by applicant]
US 10236390B2 · Yamane et al. · 2019 [cited by applicant]
US 10367005B2 · Yamazaki et al. · 2019 [cited by applicant]
US 10424671B2 · Yamazaki et al. · 2019 [cited by applicant]
US 10475931B2 · Yamazaki · 2019 [cited by applicant]
US 10727356B2 · Yamazaki · 2020 [cited by applicant]
US 20170062619A1 · Sasagawa · 2017 [cited by examiner]
US 20170278855A1 · Liaw · 2017 [cited by examiner]
US 20200105883A1 · Yamazaki et al. · 2020 [cited by applicant]
US 20200144310A1 · Onuki et al. · 2020 [cited by applicant]
US 20200227561A1 · Yamazaki · 2020 [cited by applicant]
CN 107980178A · 2018 [cited by applicant]
CN 108886021A · 2018 [cited by applicant]
CN 109478514A · 2019 [cited by applicant]
CN 110462803A · 2019 [cited by applicant]
DE 112018001745 · 2019 [cited by applicant]
JP 2011151383A · 2011 [cited by applicant]
JP 2012257187A · 2012 [cited by applicant]
JP 2018181890A · 2018 [cited by applicant]
JP 2018195814A · 2018 [cited by applicant]
KR 20190133024A · 2019 [cited by applicant]
TW 201822286 · 2018 [cited by applicant]
TW 201901971 · 2019 [cited by applicant]
WO WO2017033102 · 2017 [cited by applicant]
WO WO2017137864 · 2017 [cited by applicant]
WO WO2018020350 · 2018 [cited by applicant]
WO WO2018178806 · 2018 [cited by applicant]
WO WO2018207048 · 2018 [cited by applicant]
Taiwanese Office Action (Application No. 109122285) Dated Feb. 21, 2024. [cited by applicant]
International Search Report (Application No. PCT/IB2020/056149) Dated Oct. 6, 2020. [cited by applicant]
Written Opinion (Application No. PCT/IB2020/056149) Dated Oct. 6, 2020. [cited by applicant]
Chinese Office Action (Application No. 202080047776.2) dated Oct. 31, 2024. [cited by applicant]