SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.
1. An apparatus comprising:
a cache unit having a global supply line and a plurality of subcache units including a first subcache unit and a second subcache unit, wherein the first subcache unit comprises a row and a column, and wherein the second subcache unit comprises a row and a column; and
a plurality of write assist circuitries including a first write assist circuitry and a second write assist circuitry,
wherein:
the first write assist circuitry is coupled to the global supply line and a first local supply line;
the second write assist circuitry is coupled to the global supply line and a second local supply line;
the first local supply line is to provide a first supply to the first subcache unit;
the second local supply line is to provide a second supply to the second subcache unit; and
the first write assist circuitry comprises a transistor coupled to the global supply line, and wherein the transistor comprises a diode-connected transistor.
2. The apparatus of claim 1 , wherein the first and second subcache units comprise an SRAM.
3. The apparatus of claim 1 , wherein the first write assist circuitry comprises:
a second transistor coupled to the first local supply line and to the transistor.
4. The apparatus of claim 1 comprises a write driver to drive data onto the first subcache unit.
5. The apparatus of claim 1 comprises a column selector coupled to the first subcache unit.
6. The apparatus of claim 1 comprises read/write local column multiplexers which include pass--gates to provide electrical coupling of global read and write data lines to generate local read and write signals.
7. A method comprising:
forming a cache unit having a global supply line and a plurality of subcache units including a first subcache unit and a second subcache unit, wherein the first subcache unit comprises a row and a column, and wherein the second subcache unit comprises a row and a column;
forming a plurality of write assist circuitries including a first write assist circuitry and a second write assist circuitry;
coupling the first write assist circuitry to the global supply line and a first local supply line;
coupling the second write assist circuitry to the global supply line and a second local supply line;
providing a first supply on the first local supply line to the first subcache unit;
providing a second supply on the second supply line to the second subcache unit;
forming a transistor; and
coupling the transistor to the global supply line, wherein the transistor comprises a diode-connected transistor.
8. The method of claim 7 , wherein the first and second subcache units comprise an SRAM.
9. The method of claim 7 , wherein forming the first write assist circuitry comprises:
forming a second transistor; and
coupling the second transistor to the first local supply line and to the first transistor.
10. The method of claim 7 comprises forming a write driver to drive data onto the first subcache unit.
11. The method of claim 7 comprises forming a column selector coupled to the first subcache unit.
12. The method of claim 7 comprises forming read/write local column multiplexers which include pass-gates to provide electrical coupling of global read and write data lines to generate local read and write signals.
13. An apparatus comprising:
cache means having a global supply line and a plurality of subcache units including a first subcache unit and a second subcache unit, wherein the first subcache unit comprises a row and a column, and wherein the second subcache unit comprises a row and a column;
a plurality of write assist means including a first write assist circuitry and a second write assist circuitry;
means for coupling the first write assist circuitry to the global supply line and a first local supply line;
means for coupling the second write assist circuitry to the global supply line and a second local supply line;
means for providing a first supply on the first local supply line to the first subcache unit;
means for providing a second supply on the second local supply line to the second subcache unit; and
read/write local column multiplexer means to provide electrical coupling of global read and write data lines to generate local read and write signals.
14. The apparatus of claim 13 , wherein the first and second subcache units comprise an SRAM.
15. The apparatus of claim 13 , wherein the first write assist means comprise:
a first transistor;
coupling means for coupling the first transistor to the global supply line, wherein the first transistor comprises a diode-connected transistor;
a second transistor; and
coupling means for coupling the second transistor to the first local supply line and to the first transistor.
16. The apparatus of claim 13 comprises write driver means to drive data onto the first subcache unit.
17. The method of claim 13 comprises a column selector means coupled to the first subcache unit.
18. The method of claim 13 , wherein the read/write local column multiplexer means include pass-gates to provide the electrical coupling of the global read and write data lines to generate the local read and write signals.
19. A system comprising:
a processor;
a memory coupled to the processor, the memory comprising:
a cache unit having a global supply line and a plurality of subcache units including a first subcache unit and a second subcache unit, wherein the first subcache unit comprises a row and a column, and wherein the second subcache unit comprises a row and a column; and
a plurality of write assist circuitries including a first write assist circuitry and a second write assist circuitry,
wherein:
the first write assist circuitry is coupled to the global supply line and a first local supply line;
the second write assist circuitry is coupled to the global supply line and a second local supply line;
the first local supply line is to provide a first supply to the first subcache unit;
the second local supply line is to provide a second supply to the second subcache unit; and
the write assist circuitry comprises a transistor coupled to the global supply line, and wherein the transistor is comprises a diode-connected transistor; and
a wireless interface to allow the processor to communicate with another device.
20. The system of claim 19 comprises a display communicatively coupled to the processor.
21. The system of claim 19 , wherein the first and second subcache units comprise an SRAM.
22. The system of claim 19 , wherein the first write assist circuitry comprises:
a second transistor coupled to the first local supply line and to the first transistor.
23. The system of claim 19 , wherein the memory comprises:
a write driver to drive data onto the first subcache unit;
a column selector coupled to the first subcache unit; and
read/write local column multiplexers which include pass-gates to provide electrical coupling of global read and write data lines to generate local read and write signals.