Impedance and swing control for voltage-mode driver
A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.
1. A driver circuit, comprising:
a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node, each of the plurality of output circuits comprising:
a series combination of a pair of enable circuits, a pair of inverters, and a pair of resistors, coupled between the differential input and the differential output;
a first transistor coupled between the first common node and first source terminals of the pair of inverters; and
a second transistor coupled between the second common node and second source terminals of the pair of inverters;
first and second replica output circuits coupled in series between the first and second common nodes; and
a control circuit coupled to each of: respective gates of the first and second transistors in each of the plurality of output circuits; and the first and second replica output circuits.
2. The driver circuit of claim 1 , further comprising:
a replica load resistor coupled in series between the first and second replica output circuits.
3. The driver circuit of claim 2 , wherein:
the first replica output circuit comprises a first replica transistor, a second replica transistor, and a first replica resistor serially connected to provide a current path between the first common node and the replica load resistor; and
the second replica output circuit comprises a third replica transistor, a fourth replica transistor, and a second replica resistor serially connected to provide a current path between the replica load resistor and the second common node.
4. The driver circuit of claim 3 , wherein the control circuit comprises:
a first operational amplifier having a first terminal coupled to a first switched resistor network, a second terminal coupled to a node between the first replica resistor and the replica load resistor, and an output terminal coupled to each of: a gate of the first replica transistor; and gate of the first transistor in each of the plurality of output circuits; and
a second operational amplifier having a first terminal coupled to a second switched resistor network, a second terminal coupled to a node between the second replica resistor and the replica load resistor, and an output terminal coupled to each of: a gate of the fourth replica transistor; and gate of the second transistor in each of the plurality of output circuits.
5. The driver circuit of claim 4 , wherein the first switched resistor network is coupled between the first common node and a reference resistor, and wherein the second switched resistor network is coupled between the reference resistor and the second common node.
6. The driver circuit of claim 5 , wherein the first switched resistor network comprises a first plurality of taps and a first switch coupled between the first plurality of taps and the first terminal of the first operational amplifier, and wherein the second switched resistor network comprises a second plurality of taps and a second switch coupled between the second plurality of taps and the first terminal of the second operational amplifier.
7. The driver circuit of claim 4 , wherein the second replica output circuit further comprises:
a startup circuit coupled to the output terminal of the second operational amplifier.
8. The driver circuit of claim 1 , wherein the pair of enable circuits in each of the plurality of output circuits each comprises a NAND gate and a NOR gate.
9. The driver circuit of claim 1 , further comprising:
a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; and
a second voltage regulator having an output coupled to the second common node of the plurality of circuits.
10. The driver circuit of claim 9 , further comprising:
a first capacitor coupled between the first common node of the plurality of output circuits and a ground source; and
a second capacitor coupled between the second common node of the plurality of output circuits and the ground source.
11. The driver circuit of claim 1 , wherein the differential output of the plurality of output circuits is coupled to a pair of transmission lines.