Low power driver scheme for on-chip and interposer based data transmission
Signal routing and EMIR requirements are causing increased demand for metal resources. The cost of metal resources is also an issue. The design and sign-off of on-chip drivers for driving signals from one chip location to another is complicated by requirements for power integrity and signal routing. This disclosure addresses routing resource bottlenecks and power requirements by introducing a low power driver useable in a high speed SERDES scheme. A voltage clipping high speed and low swing driver is disclosed. Threshold switching voltage of the transmitted signal is controlled by a process and temperature compensated biasing scheme. A reference voltage generation circuitry along with a simple receiver demonstrates the capability of this receiver. This transceiver scheme can be used on an on-chip or off-chip SERDES application to send/receive low speed signals serially. Use of this novel technique addresses the metal resource issue along with EMIR and SIPI requirements.
1 . A method, comprising:
converting, in a voltage-controlled driver, standard voltage threshold parallel data to serialized non-return-to-zero data;
biasing, using p-bias generator circuitry of a bias generator, p-channel devices of the driver to control pull-down voltage levels;
biasing, using n-bias generator circuitry of the bias generator, n-channel devices of the driver to control pull-up voltage levels, wherein the pull-down voltage levels and the pull-up voltage levels, collectively, are configured to adjust a threshold switching voltage;
transmitting the serialized non-return-to-zero data on a transmission channel to a receiver-deserializer, the receiver-deserializer including a pre-amplifier and an amplifier; and
converting the serialized non-return-to-zero data to standard voltage threshold parallel data.
2 . The method of claim 1 , further comprising providing a transmission channel connecting a first chip and a second chip.
3 . The method of claim 1 , further comprising transmitting serialized, non-return-to-zero differential voltage data.
4 . The method of claim 1 , wherein the p-channel devices and the n-channel devices are compensated for process variation and temperature variation such that the threshold switching voltage is adjusted only based on the pull-down voltage levels and the pull-up voltage levels.
5 . The method of claim 1 , wherein the pre-amplifier includes current limiting circuitry and equalization circuitry.
6 . The method of claim 5 , wherein the current limiting circuitry includes a first p-channel transistor and a first resistor in a first branch and a second p-channel transistor and a second resistor in a second branch, and equalization circuitry includes a capacitor and a third resistor.
7 . A device, comprising:
an input for standard voltage threshold parallel data in a pre-driver;
a non-return-to-zero voltage-controlled driver coupled to the pre-driver; wherein the non-return-to-zero voltage-controlled driver is configured to convert standard voltage threshold parallel data to serialized non-return-to-zero data;
a bias generator coupled to the non-return-to-zero voltage-controlled driver, the bias generator including p-bias generator circuitry configured to bias p-channel devices of the driver to control pull-down voltage levels and n-bias generator circuitry configured to bias n-channel devices of the driver to control pull-up voltage levels, wherein the pull-down voltage levels and the pull-up voltage levels, collectively, are configured to adjust a threshold switching voltage;
a transmission channel; and
a data output in a receiver coupled to the transmission channel, wherein the receiver is configured to convert the serialized non-return-to-zero data to standard voltage threshold parallel data, the receiver including a pre-amplifier and an amplifier.
8 . The device of claim 7 , wherein the pre-amplifier includes current limiting circuitry and equalization circuitry.
9 . The device of claim 8 , wherein the current limiting circuitry includes a first p-channel transistor and a first resistor in a first branch and a second p-channel transistor and a second resistor in a second branch, and the equalization circuitry includes a capacitor and a third resistor.
10 . The device of claim 7 , further comprising a reference voltage generator configured to generate a reference voltage close to the threshold switching voltage.
11 . A device, comprising:
a non-return-to-zero voltage-controlled driver configured to convert standard voltage threshold parallel data to serialized non-return-to-zero data; and
a bias generator including p-bias generator circuitry configured to bias p-channel devices of the driver to control pull-down voltage levels and n-bias generator circuitry configured to bias n-channel devices of the driver to control pull-up voltage levels, wherein the pull-down voltage levels and the pull-up voltage levels, collectively, are configured to adjust a threshold switching voltage; and
a transmission channel from the non-return-to-zero voltage-controlled driver to a receiver-deserializer, wherein the receiver-deserializer is configured to convert non-return-to-zero data to standard voltage threshold parallel data.
12 . The device of claim 11 , wherein the transmission channel further comprises:
a channel connecting a first chip and a second chip.
13 . The device of claim 11 , wherein the serialized non-return-to-zero data further comprises serialized, non-return-to-zero differential voltage data.
14 . The device of claim 11 , wherein the p-channel devices and the n-channel devices are compensated for process variation and temperature variation such that the threshold switching voltage is adjusted only based on the pull-down voltage levels and the pull-up voltage levels.
15 . The device of claim 11 , wherein the receiver-deserializer includes a pre-amplifier and an amplifier, the amplifier including current limiting circuitry and equalization circuitry.
16 . The device of claim 15 , wherein the current limiting circuitry includes a first p-channel transistor and a first resistor in a first branch and a second p-channel transistor and a second resistor in a second branch, and the equalization circuitry includes a capacitor and a third resistor.
17 . The device of claim 11 , wherein the standard voltage threshold parallel data comprises CMOS voltage levels.
18 . The device of claim 11 , further comprising:
a pre-driver coupled to the non-return-to-zero voltage-controlled driver; and
a reference voltage generator coupled to the receiver-deserializer.
19 . The device of claim 18 , wherein the bias generator is configured to supply the threshold switching voltage of the transmitted non-return-to-zero data.
20 . The device of claim 18 , wherein the reference voltage generator is configured to generate a reference voltage close to the threshold switching voltage.