Method and apparatus for passive continuous-time linear equalization with continuous-time baseline wander correction
Described is an apparatus which comprises: a first capacitor coupled to a first input pad; a second capacitor coupled to second input pad; a first resistor coupled to the second capacitor; a third capacitor coupled in series with the first resistor; a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and a differential amplifier coupled to the first and second capacitors and to the first and second resistors.
1. An apparatus comprising:
a first capacitor coupled to a first input pad;
a second capacitor coupled to second input pad;
a first resistor coupled to the second capacitor;
a third capacitor coupled in series with the first resistor;
a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and
a differential amplifier coupled to the first and second capacitors and to the first and second resistors.
2. The apparatus of claim 1 comprises:
a third resistor coupled to: the first capacitor, the second resistor, and the differential amplifier; and
a fourth resistor coupled to: the third resistor, the first input pad, and the first capacitor.
3. The apparatus of claim 2 comprises:
a fifth resistor coupled to: the second capacitor, the first resistor, and the differential amplifier; and
a sixth resistor coupled to: the fifth resistor, the second input pad, and the second capacitor.
4. The apparatus of claim 3 comprises: a seventh resistor coupled to: the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor.
5. The apparatus of claim 4 comprises:
an eighth resistor coupled to: the seventh resistor, the third resistor, and the fourth resistor; and
a ninth resistor coupled to: the seventh resistor, the fifth resistor and the sixth resistor.
6. The apparatus of claim 5 comprises:
an offset correction circuitry;
a first unity gain amplifier coupled to the offset correction circuitry and the eighth resistor; and
a second unity gain amplifier coupled to the offset correction circuitry and the ninth resistor.
7. The apparatus of claim 1 , wherein the differential amplifier has a differential output coupled to a decision feedback equalizer.
8. The apparatus of claim 1 comprises a first termination resistor coupled to the first input pad and to ground.
9. The apparatus of claim 1 comprises a second termination resistor coupled to the second input pad and to ground.
10. An apparatus comprising:
a first capacitor coupled to a first input pad;
a second capacitor coupled to second input pad which is coupled to a ground node;
a first resistor coupled to the second capacitor;
a third capacitor coupled in series with the first resistor and to the ground node;
a second resistor coupled to the first capacitor;
a fourth capacitor coupled in series with the second resistor and to the ground node; and
a differential amplifier coupled to the first and second capacitors and to the first and second resistors.
11. The apparatus of claim 10 comprises:
a third resistor coupled to: the differential amplifier, the first resistor, and the second capacitor; and
a fourth resistor couples to: the third resistor, the second capacitor, and to the second input pad.
12. The apparatus of claim 11 comprises:
a fifth resistor coupled to: the differential amplifier, the second resistor, and the first capacitor; and
a sixth resistor couples to: the fifth resistor, the first capacitor, and to the first input pad.
13. The apparatus of claim 12 comprises:
a seventh resistor coupled to the third resistor and the fourth resistor; and
an eighth resistor coupled to the fifth resistor and the sixth resistor.
14. The apparatus of claim 13 comprises:
ninth resistor coupled to the seventh and fourth resistor; and
tenth resistor coupled to the eighth and sixth resistor.
15. The apparatus of claim 14 comprises:
an offset correction circuitry;
a first unity gain amplifier coupled to the offset correction circuitry and the ninth resistor; and
a second unity gain amplifier coupled to the offset correction circuitry and the tenth resistor.
16. The apparatus of claim 10 , wherein the differential amplifier has a differential output coupled to a decision feedback equalizer.
17. The apparatus of claim 1 comprises:
a first termination resistor coupled to the first input pad and to ground; and
a second termination resistor coupled to the second input pad and to ground.
18. A system comprising:
a memory;
a processor coupled to the memory, the processor having a receiver including:
a first capacitor coupled to a first input pad;
a second capacitor coupled to second input pad;
a first resistor coupled to the second capacitor;
a third capacitor coupled in series with the first resistor;
a second resistor coupled in series with the third capacitor and also coupled to the first capacitor; and
a differential amplifier coupled to the first and second capacitors and to the first and second resistors; and
a wireless interface to allow the processor to communicate with another device.
19. The system of claim 18 , wherein the receiver is at least part of one of:
Peripheral Component Interconnect (PCI) compliant receiver;
Serial AT Attachment (SATA) compliant receiver; or
Universal Serial Bus (USB) compliant receiver.
20. The system of claim 18 , wherein the processor comprises a reference voltage provider to provide a common mode reference voltage to the receiver.