Granted Patent B2

US 12,483,449 · App. 18/162,337 · Granted Nov 25, 2025

Inventors: Siamak Delshadpour (Phoenix, AZ); Alexander Wayne Sheldon (Gilbert, AZ)

Assignee: NXP USA, Inc.

H04L25/03885H04L25/0272H04L25/03031

Abstract

Claims (44)

1 . A passive equalizer circuit, comprising:

an input configured to receive an input signal having an input frequency band;

a transfer function circuit configured to transform the input frequency band into an output frequency band; and

an output configured to be coupled to an active equalizer circuit and carry an output signal having the output frequency band;

wherein the transfer function circuit includes a variable impedance circuit configured to adjust a mid-band frequency gain of the output signal;

wherein the variable impedance circuit includes a first variable capacitor (C 4 ) having a variable capacitance in parallel with the active equalizer circuit;

wherein the first variable capacitor adjusts a set of mid-band frequency gains of the output frequency band;

wherein the first variable capacitor is in parallel with a first resistor (R 4 ) having a resistance and in series with a second resistor (R 3 ) having a resistance; and

wherein the second resistor (R 3 ) is coupled to the output.

2 . The passive equalizer circuit of claim 1 :

wherein the passive equalizer circuit includes only passive resistive, and/or capacitive elements.

3 . The passive equalizer circuit of claim 1 :

wherein a value of the first variable capacitor is statically trimmed using a set of one-time-adjustable passive elements.

4 . The passive equalizer circuit of claim 1 :

wherein a value of the first variable capacitor is dynamically trimmed using a controller.

5 . The passive equalizer circuit of claim 1 :

wherein the first variable capacitor includes a set of switches each coupled in series with a separate capacitor; and

wherein an open and closed state of the set of switches adjusts the first variable capacitor.

6 . The passive equalizer circuit of claim 1 :

wherein a pole of the set of mid-band frequency gains is equal to 1/(R 4 *C 4 ).

7 . The passive equalizer circuit of claim 1 :

wherein the variable impedance circuit further includes a second variable capacitor (C 2 ) having a variable capacitance in series with the active equalizer circuit; and

wherein the second variable capacitor adjusts a zero frequency of the output frequency band.

8 . The passive equalizer circuit of claim 7 :

wherein the first variable capacitor includes a first set of switches each coupled in series with a separate capacitor;

wherein an open and closed state of the first set of switches adjusts the first variable capacitor;

wherein the second variable capacitor includes a second set of switches each coupled in series with a separate capacitor; and

wherein an open and closed state of the second set of switches adjusts the second variable capacitor.

9 . The passive equalizer circuit of claim 7 :

wherein the second variable capacitor is in parallel with a third resistor (R 2 ) having a resistance and in series with a fourth resistor (R 1 ) having a resistance;

wherein the fourth resistor (R 1 ) is coupled to the input; and

wherein the third resistor (R 2 ) and the second variable capacitor are coupled to the output.

10 . The passive equalizer circuit of claim 9 :

wherein a ratio of the first (R 4 ) to the second resistance (R 3 ) is equal to a ratio of the third resistance (R 2 ) to the fourth resistance (R 1 ).

11 . The passive equalizer circuit of claim 9 :

wherein a zero of the set of mid-band frequency gains is equal to 1/(R 2 *C 2 ).

12 . The passive equalizer circuit of claim 1 :

further comprising the active equalizer circuit coupled to the passive equalizer circuit.

13 . The passive equalizer circuit of claim 1 :

wherein the active equalizer circuit is a continuous-time linear equalizer (CTLE).

14 . The passive equalizer circuit of claim 1 :

wherein the active equalizer circuit is a linear equalizer.

15 . The passive equalizer circuit of claim 1 :

wherein the active equalizer circuit is a decision-feedback equalizer (DFE).

Assignments (1)

Continuity (1)

References Cited (24)