Method of forming a temporary test structure for device fabrication
A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.
1. A method of forming a temporary test structure for device fabrication comprising:
providing a substrate having a device side and a grind side, and comprising a plurality of through-silicon vias (TSVs) extending vertically to a top surface of the device side with a layer of a first insulating polymer covering the top surface except surfaces of the plurality of TSVs;
conformally forming a first electrical test layer on the top surface of the device side, the first electrical test layer connecting to the plurality of TSVs;
patterning the first electrical test layer by selectively removing portions of the first electrical test layer to form a first temporary test structure which comprises unremoved portions of the first electrical test layer;
applying a layer of a first adhesive over the top surface of the device side of the substrate, bonding a layer of a first carrier using the layer of the first adhesive, and flipping the substrate upside down;
thinning the grind side of the substrate to reveal the plurality of TSVs;
forming a layer of a second insulating polymer on a top surface of the grind side with an insulating-layer pattern not covering surfaces of the plurality of TSVs;
conformally forming a second electrical test layer on the top surface of the grind side, the second electrical test layer connecting to the plurality of TSVs;
patterning the second electrical test layer by selectively removing portions of the second electrical test layer to form a second temporary test structure which comprises unremoved portions of the second electrical test layer and comprises providing electrical connection between at least a first test location and a second test location, wherein the first and second test locations are each electrically connected to at least one of the plurality of TSVs;
performing electrical testing by probing at least the first test location and the second test location on the second temporary test structure;
removing the second temporary test structure;
applying a layer of a second adhesive over the top surface of the grind side of the substrate, bonding a layer of a second carrier using the layer of the second adhesive, and flipping the substrate upside down;
debonding the layer of the first carrier and removing the layer of the first adhesive to reveal the first temporary test structure; and
removing the first temporary test structure;
wherein patterning the first electrical test layer, patterning the second electrical test layer, or patterning both comprises:
performing a laser ablation on the first or second electrical test layer using an excimer laser through an ablation mask, which comprises an electrical testing pattern, to selectively remove portions of the first or second electrical test layer; and
removing loose material of the first or second electrical test layer to form the corresponding first or second temporary test structure comprising the electrical testing pattern;
wherein the first electrical test layer and the second electrical test layer comprises titanium tungsten alloy (Ti—W) in a single layer, or comprises copper (Cu) or Cu alloy over titanium or titanium tungsten alloy (Ti—W) in a bilayer; and
wherein a thickness of the first electrical test layer and the second electrical test layer comprises about 20 nm to 1200 nm.