IP Library Granted Patent US 10,056,482
Granted Patent B2
US 10,056,482 · App. 15/485,457 · Granted Aug 21, 2018

Implementation of long-channel thick-oxide devices in vertical transistor flow

Inventors: Karthik Balakrishnan (White Plains, NY); Kangguo Cheng (Schenectady, NY); Pouya Hashemi (White Plains, NY); Alexander Reznicek (Troy, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/7827H01L21/76224H01L21/823412H01L21/823437H01L21/823481H01L21/823487H01L27/088H01L29/0649H01L29/0847H01L29/6656H01L29/66545H01L29/66666
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Quick Facts
Patent No.
US 10,056,482
App. No.
15/485,457
Granted
Aug 21, 2018
Kind
B2
Abstract

A method for fabricating a semiconductor structure is provided that includes the steps of: forming a structure including a substrate, a counter-doped layer on the substrate, and a heavily doped source contact layer on a side of the counter-doped layer opposite the substrate; and forming an oxide layer on a side of the heavily doped source contact layer opposite the counter-doped layer, wherein the oxide layer has a vertical dimension that is a difference between a length of a long channel thick oxide device and a length of a short channel non-thick oxide device.

Claims (12)

1. A semiconductor structure comprising:

a substrate;

a first vertical transistor device having a first region on a doped source contact layer of the substrate and having a first drain; and

a second vertical transistor device having a second region on the doped source contact layer of the substrate and having a second drain;

wherein the first vertical transistor device comprises a short vertical channel, and the second vertical transistor device comprises a long vertical channel having a vertical length greater than the short vertical channel.

2. The semiconductor structure of claim 1 , wherein the long vertical channel comprises an oxide having an equivalent oxide thickness of about 1 to about 5 nanometers.

3. The semiconductor structure of claim 1 , further comprising a metal gate in contact with sidewalls of a first epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer:

wherein the first spacer layer and the second spacer layer are separate and do not touch.

4. A semiconductor structure comprising:

a source contact layer formed on a substrate, the source contact layer comprising a first thickness in a first region of the substrate and a second thickness in a second region of the substrate, the first thickness greater than the second thickness;

a short channel, non-thick oxide vertical transistor device formed on a surface of the source contact layer in the first region of the substrate; and

a long channel, thick oxide vertical transistor device formed on a surface of the source contact layer in the second region of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2017
From: BALAKRISHNAN, KARTHIK; CHENG, KANGGUO; HASHEMI, POUYA; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041982/0579 →
Continuity (2)
Division 14979939 · Dec 28, 2015
Related Publication 20170222048A1 · Aug 3, 2017