Method and apparatus for correcting errors on a wafer processed by a photolithographic mask

1. A method for correcting at least one error on wafers processed by at least one template for a nanoimprint lithography, the method comprising:

a. measuring the at least one overlay error on a wafer at a wafer processing site;

b. modifying a global overlay error of the at least one overlay error of the at least one template for the nanoimprint lithography by a linear transformation; and

c. modifying a local overlay error of the at least one overlay error of the at least one template for the nanoimprint lithography by introducing at least one arrangement of local persistent modifications in the at least one template for the nanoimprint lithography.

2. The method according to claim 1 , wherein the at least one overlay error comprises at least one error of at least one of at least two templates for the nanoimprint lithography used in a multiple patterning lithography process.

3. The method according to claim 1 , wherein measuring of the at least one error comprises measuring of the at least one error in the active area of a chip (in-die).

4. The method according to claim 3 , wherein in-die measuring of the at least one overlay error comprises measuring of at least one of: a shift of at least one two-dimensional structure on a wafer, a shift of at least one three-dimensional structure on a wafer, an ellipticity of at least one two-dimensional structure with an imaging-based or a model-based metrology method, or an ellipticity of at least one three-dimensional structure with an imaging based or a model-based metrology method.

5. The method according to claim 1 , wherein the overlay error comprises at least one local overlay error of at least one first template for the nanoimprint lithography and at least one second template for the nanoimprint lithography, the method further comprising the step of:

correcting the at least one local overlay error by introducing at least one arrangement of local persistent modifications in the at least one first template and/or the at least one second template so that the at least one overlay error is minimized.

6. The method according to claim 5 , wherein correcting the at least one local overlay error comprises introducing at least one first arrangement of local persistent modifications in the at least one first template and/or introducing at least one second arrangement of local persistent modifications in the at least one second template.

7. The method according to claim 5 , wherein the at least one overlay error comprises at least one critical dimension uniformity error of the first template and/or at least one pattern placement error of the second template in a multiple patterning lithography process.

8. The method according to claim 1 , wherein measuring the at least one error on the wafer comprises:

a. generating a test mask having a test pattern;

b. printing and etching the test pattern of the test mask on the wafer;

c. printing and etching a template pattern on the test pattern of the wafer; and

d. determining the at least one error as a difference of at least one pattern element of the template for the nanoimprint lithography and the at least one respective test pattern element of the test mask.

9. The method according to claim 8 , wherein printing and etching of the test mask and printing and etching of the template pattern comprises a single patterning or a multiple patterning lithography process.

10. The method according to claim 8 , further comprising the step of determining an overlay error from a shift of a plurality of test pattern elements of the test mask relative to pattern elements of the template.

11. The method according to claim 1 , further comprising the step of introducing the at least one arrangement of local persistent modifications in a sacrificial layer on the wafer used in a self-aligned double patterning process.

12. An apparatus for correcting at least one overlay error on wafers processed by at least one template for a nanoimprint lithography, comprising:

a. at least one metrology system located in a wafer processing site and/or in a mask shop and adapted to measure the at least one overlay error on a wafer;

b. at least one computing means adapted to calculate parameters for at least two error correcting means based on the at least one overlay error;

c. at least one first error correcting means adapted for modifying a local overlay error of the at least one overlay error by introducing at least one arrangement of local persistent modifications in the template for the nanoimprint lithography by applying ultra-short light pulses; and

d. at least one second error correcting means adapted for modifying a global overlay error of the at least one overlay error by performing a linear transformation.

13. The apparatus according to claim 12 , wherein the apparatus is adapted to correct at least one error on wafers processed by at least one template for the nanoimprint lithography by:

a. measuring the at least one error on the wafer at a wafer processing site;

b. modifying a global overlay error of the at least one overlay error of the at least one template by a linear transformation; and

c. modifying a local overlay error of the at least one overlay error or the at least one template for the nanoimprint lithography by introducing at least one arrangement of local persistent modifications in the at least one template for the nanoimprint lithography.

14. The apparatus according to claim 12 , wherein the at least one metrology system comprises an ultrahigh-precision stage, at least one laser source or at least one other light source, at least one charge-coupled device camera operating in the ultraviolet wavelength range, a scanning electron microscope or a scatterometer, and an image-based or a model-based metrology system.

15. The apparatus according to claim 12 , wherein the at least one overlay error comprises at least one error of at least one of at least two templates for the nanoimprint lithography used in a multiple patterning lithography process.

16. The apparatus according to claim 12 , wherein the at least one overlay error comprises at least one error in the active area of a chip (in-die).

17. The apparatus according to claim 16 , wherein the at least one metrology system is adapted to measure at least one of a shift of at least one two-dimensional structure on a wafer, a shift of at least one three-dimensional structure on a wafer, an ellipticity of at least one two-dimensional structure, or an ellipticity of at least one three-dimensional structure, with at least one of an imaging-based or a model-based metrology method.

18. The apparatus according to claim 12 , wherein the overlay error comprises at least one local overlay error of at least one first template for nanoimprint lithography and at least one second template for nanoimprint lithography, and the apparatus is adapted to correct the at least one local overlay error by introducing at least one arrangement of local persistent modifications in the at least one first template and/or in the at least second template so that the at least one overlay error is minimized.

19. The apparatus according to claim 18 , wherein the apparatus is adapted to correct the at least one local overlay error by introducing at least one first arrangement of local persistent modifications in the at least one first template and/or introducing at least one second arrangement of local persistent modifications in the at least one second template.

20. The apparatus according to claim 18 , wherein the at least one overlay error comprises at least one critical dimension uniformity error of the first template and/or at least one pattern placement error of the second template in a multiple patterning lithography process.

21. The apparatus according to claim 12 , wherein the at least one metrology system is adapted to measure the at least one overlay error on the wafer by determining the at least one overlay error as a difference of at least one pattern element of the template for the nanoimprint lithography and at least one respective test pattern element of a test mask.

22. The apparatus according to claim 21 , wherein the at least one metrology system is adapted to determine an overlay error from a shift of a plurality of test pattern elements of the test mask relative to pattern elements of the template.

23. The apparatus according to claim 12 , wherein at least one first error correcting means is adapted for introducing the at least one arrangement of local persistent modifications in a sacrificial layer on the wafer used in a self-aligned double patterning process.