IP Library › Granted Patent US 10,062,613
Granted Patent B1
US 10,062,613 · App. 15/611,759 · Granted Aug 28, 2018

Semiconductor device and method for fabricating the same

Inventors: Feng-Yi Chang (Tainan, TW); Shih-Fang Tzou (Tainan, TW); Yu-Cheng Tung (Kaohsiung, TW); Ming-Feng Kuo (Tainan, TW); Li-Chiang Chen (Tainan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L21/823456H01L21/82345H01L21/823481H01L27/10823H01L27/10876
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Quick Facts
Patent No.
US 10,062,613
App. No.
15/611,759
Granted
Aug 28, 2018
Kind
B1
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate; forming a first work function metal layer in the first trench and the second trench; forming a patterned mask to cover the second trench; removing the first work function metal layer from the first trench; forming a second work function metal layer in the first trench and the second trench; and forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.

Claims (21)

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

removing part of the substrate to form a first trench and a second trench in the substrate;

forming a first work function metal layer in the first trench and the second trench;

forming a patterned mask to cover the second trench;

removing the first work function metal layer from the first trench;

forming a second work function metal layer in the first trench and the second trench; and

forming a conductive layer in the first trench and the second trench to form a first gate structure and a second gate structure.

2. The method of claim 1 , further comprising:

forming a gate dielectric layer in the first trench and the second trench; and

forming the first work function metal layer on the gate dielectric layer.

3. The method of claim 1 , wherein the patterned mask comprises an organic layer.

4. The method of claim 1 , further comprising:

removing the patterned mask after removing the first work function metal layer; and

forming the second work function metal layer in the first trench and the second trench.

5. The method of claim 1 , wherein the top surfaces of the first gate structure and the second gate structure are coplanar.

6. The method of claim 1 , further comprising forming a shallow trench isolation (STI) in the first trench before forming the first work function metal layer.

7. The method of claim 6 , wherein a top surface of the STI is lower than a bottom surface of the second trench.

8. The method of claim 1 , further comprising forming a hard mask on each of the first gate structure and the second gate structure after forming the conductive layer.

9. The method of claim 8 , wherein the top surfaces of the hard mask and the substrate are coplanar.

10. The method of claim 8 , wherein the hard mask comprises silicon nitride.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 9, 2020
From: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
To: FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 054367/0768 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2017
From: CHANG, FENG-YI; TZOU, SHIH-FANG; TUNG, YU-CHENG; KUO, MING-FENG; CHEN, LI-CHIANG
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 042569/0356 →
Priority Claims (1)
CN 2017 1 0308679 · May 4, 2017 · national
Cited By (2)
US 12,641,775 US 12,740,049