Semiconductor memory device
A semiconductor memory device is provided. The semiconductor device may include a semiconductor substrate having a device isolation trench defining active regions, a device isolation layer disposed in the device isolation trench, gate trenches extending in a first direction and crossing the active regions of the semiconductor substrate and the device isolation layer, word lines disposed in the gate trenches, respectively, each of the gate trenches may include first trench sections in the active regions and second trench sections in the device isolation layer, the first trench sections may have a first depth, and the second trench section may have a second depth greater than the first depth, the device isolation layer may include a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and the lower portion may be formed of a dielectric material having a lower dielectric constant than that of the upper portion.
1 . A semiconductor device comprising:
a semiconductor substrate having a device isolation trench defining active regions;
a device isolation layer disposed in the device isolation trench;
gate trenches extending in a first direction with each gate trench crossing a respective plurality of the active regions of the semiconductor substrate and the device isolation layer; and
word lines disposed in the gate trenches, respectively,
wherein each of the gate trenches includes first trench sections in respective active regions and a second trench section in the device isolation layer, the first trench sections have a first depth, and the second trench section has a second depth greater than the first depth,
wherein the device isolation layer includes a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion,
wherein the lower portion of the device isolation layer is formed of a dielectric material having a lower dielectric constant than that of the upper portion, and
wherein an upper surface of the dielectric material having a lower dielectric constant than that of the upper portion is positioned at a level between the bottom surfaces of the first trench sections and a bottom surface of the second trench section.
2 . The semiconductor device of claim 1 , wherein the device isolation layer includes:
a low-k dielectric pattern covering a lower sidewall of the device isolation trench;
a liner insulating pattern covering an upper sidewall of the device isolation trench; and
a buried insulating pattern on the liner insulating pattern.
3 . The semiconductor device of claim 2 , wherein the low-k dielectric pattern includes a dielectric material having a lower dielectric constant than that of the liner insulating pattern.
4 . The semiconductor device of claim 2 , wherein a portion of the liner insulating pattern covers an upper surface of the low-k dielectric pattern.
5 . The semiconductor device of claim 2 , wherein the low-k dielectric pattern includes SiC, SiCN, SiCOH, SiOC or SiOF.
6 . The semiconductor device of claim 2 , wherein the device isolation trench includes a first portion having a first width between adjacent active regions in the first direction and a second portion having a second width greater than the first width in a second direction different from the first direction, and
wherein the liner insulating pattern fills the first portion on the low-k dielectric pattern.
7 . The semiconductor device of claim 1 , wherein the device isolation layer includes:
a low-k dielectric pattern filling a lower portion of the device isolation trench; and
a liner insulating pattern covering an upper sidewall of the device isolation trench and being disposed on the low-k dielectric pattern.
8 . The semiconductor device of claim 1 , wherein the active regions are spaced apart from each other and arranged two-dimensionally, and
wherein the second trench section of each of the gate trenches is disposed between respective active regions that are adjacent to each other.
9 . The semiconductor device of claim 7 , wherein each of the word lines includes a gate conductive pattern, a gate capping pattern on the gate conductive pattern, and a gate insulating pattern between the gate conductive pattern and the semiconductor substrate, and
wherein upper surfaces of the gate conductive patterns are positioned at substantially the same level in the first trench sections and the second trench section.
10 . The semiconductor device of claim 9 , wherein an upper surface of the low-k dielectric pattern is lower than an upper surface of the gate conductive pattern and is positioned at a level higher than a bottom surface of the second trench section.
11 . The semiconductor device of claim 9 , wherein an upper portion of the gate conductive pattern in the second trench section is adjacent to the liner insulating pattern, and
wherein a lower portion of the gate conductive pattern in the second trench section is adjacent to the low-k dielectric pattern.
12 . A semiconductor device comprising:
a semiconductor substrate;
a device isolation layer disposed in the semiconductor substrate and defining active regions;
a first gate trench having a first trench section provided in the active regions and having a first depth;
a second gate trench having a second trench section provided in the device isolation layer and having a second depth greater than the first depth;
a first gate structure in the first trench section; and
a second gate structure in the second trench section,
wherein the second gate structure includes a lower portion positioned at a level lower than a bottom surface of the first trench section and an upper portion on the lower portion, and
wherein the device isolation layer includes:
a low-k dielectric pattern between the active regions and the lower portion of the second gate structure and an upper surface of the low-k dielectric pattern is positioned at a level lower than upper surfaces of the first and second gate structures and higher than a bottom surface of the second trench section; and
a liner insulating pattern between the active regions and the upper portion of the second gate structure.
13 . The semiconductor device of claim 12 , wherein the device isolation layer includes a first portion having a first width between the active regions adjacent to each other in a first direction and a second portion having a second width greater than the first width between the active regions adjacent to each other in a second direction, and
wherein the second gate structure is disposed in the second portion of the device isolation layer.
14 . The semiconductor device of claim 13 , wherein the device isolation layer further includes a buried insulating pattern on the low-k dielectric pattern in the second portion.
15 . A semiconductor device comprising:
a semiconductor substrate;
a device isolation layer disposed in the semiconductor substrate and defining active regions;
gate trenches extending in a first direction with each gate trench crossing a respective plurality of the active regions and the device isolation layer;
word lines with each word line disposed in a respective gate trench, each of the word lines including a gate conductive pattern, a gate capping pattern on the gate conductive pattern, and a gate insulating pattern between the semiconductor substrate and the gate conductive pattern;
a bit line extending in a second direction intersecting with the first direction across the word lines;
a bit line contact pattern between the bit line and the active regions;
bit line spacers disposed on sidewalls of the bit line;
contact patterns disposed on the semiconductor substrate and connected to end portions of the active regions; and
data storage patterns connected to the contact patterns,
wherein each of the gate trenches includes first trench sections in the active regions and a second trench section in the device isolation layer, and a recess depth of the second trench section is greater than a recess depth of the first trench sections,
wherein the device isolation layer includes a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and
wherein the lower portion is formed of a dielectric material having a lower dielectric constant than that of a material forming the upper portion.
16 . The semiconductor device of claim 15 , wherein the device isolation layer includes:
a low-k dielectric pattern between the active regions and a lower portion of the second trench section; and
a liner insulating pattern between the active regions and an upper portion of the second trench section.
17 . The semiconductor device of claim 15 , wherein the upper portion of the device isolation layer includes silicon oxide, and
wherein the lower portion of the device isolation layer includes SiCOH.
18 . The semiconductor device of claim 15 , wherein the lower portion of the device isolation layer includes a low-k dielectric pattern, and
Wherein the low-k dielectric pattern is positioned at a level lower than upper surfaces of the gate conductive patterns of the word lines and higher than a bottom surface of the second trench section.