FinFET device
A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm 3 within a depth range of about 0-5 nm from a surface of the strained layer.
1. A FinFET device, comprising:
a substrate having at least one fin;
a gate stack across the at least one fin;
a strained layer aside the gate stack and having a boron surface concentration greater than about 2E20 atom/cm 3 within a depth range of about 0-5 nm from a surface of the strained layer; and
a silicide layer over the strained layer.
2. The FinFET device of claim 1 , wherein the boron surface concentration of the strained layer is in a range from about 2E20 to 1E21 atom/cm 3 .
3. The FinFET device of claim 1 , wherein the boron surface concentration of the strained layer is in a range from about 1E21 to 5E21 atom/cm 3 .
4. The FinFET device of claim 1 , further comprising a lightly doped region between the gate stack and the strained layer.
5. The FinFET device of claim 4 , wherein a first portion of the lightly doped region has a boron surface concentration greater than a second portion of the lightly doped region, and the first portion is located within a depth range of about 0-5 nm from a surface of the lightly doped region, and the second portion is located below the first portion.
6. A FinFET device, comprising:
a substrate having at least one fin;
a gate stack across the at least one fin;
a strained layer aside the gate stack; and
a shallow doped region in a surface portion of strained layer, wherein a concentration of the shallow doped region is higher than a concentration of the strained layer, and the shallow doped region and the strain layer have a same conductivity type dopant,
wherein the FinFET device further comprises a lightly doped region between the gate stack and the strained layer, the lightly doped region has a first portion and a second portion below the first portion, and the first portion has a boron surface concentration greater than the second portion of the lightly doped region.
7. The FinFET device of claim 6 , wherein the shallow doped region comprises a p-type dopant.
8. The FinFET device of claim 7 , wherein the p-type dopant comprises boron.
9. The FinFET device of claim 6 , wherein the shallow doped region and the lightly doped region have a same conductivity type dopant.
10. The FinFET device of claim 6 , wherein the shallow doped region has a depth of less than about 20 nm.
11. The FinFET device of claim 6 , further comprising a spacer aside the gate stack and covering the shallow doped region.
12. The FinFET device of claim 6 , further comprising a silicide layer over the shallow doped region.
13. The FinFET device of claim 12 , further comprising at least one connector disposed on and connected to the silicide layer.
14. A FinFET device, comprising:
a substrate having at least one fin;
a metal gate stack across the at least one fin;
a source and drain region aside the metal gate stack;
a lightly doped region between the source and drain region and the metal gate stack; and
a shallow doped region in a surface portion of the source and drain region,
wherein the source and drain region, the shallow doped region and the lightly doped region have a same conductivity type dopant;
wherein a concentration of the shallow doped region is higher than a concentration of the source and drain region below the shallow doped region, and
wherein the FinFET device further comprises a spacer aside the metal stack, the lightly doped region has a first portion and a second portion with different surface concentrations, and the first portion and the second portion are in physical contact with the spacer.
15. The FinFET device of claim 14 , further comprising a silicide layer covering a portion of the shallow doped region.
16. The FinFET device of claim 14 , wherein the source and drain region comprises a strained layer.
17. The FinFET device of claim 14 , wherein the same conductivity type dopant comprises boron.