IP Library › Granted Patent US 10,068,867
Granted Patent B2
US 10,068,867 · App. 15/811,306 · Granted Sep 4, 2018

Post-passivation interconnect structure and methods thereof

Inventors: Chien-Chia Chiu (Taoyuan County, TW); Ming-Yen Chiu (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L24/14H01L21/76802H01L21/76877H01L23/528H01L23/5226H01L23/5384H01L23/5386H01L24/03H01L24/08H01L24/11H01L24/19H01L24/20H01L2224/0401H01L2224/04105H01L2224/12105H01L2224/13025H01L2224/32225H01L2224/73267H01L2924/18162
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Quick Facts
Patent No.
US 10,068,867
App. No.
15/811,306
Granted
Sep 4, 2018
Kind
B2
Abstract

A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing pad over the connective layer. The forming the connective layer includes depositing a dielectric layer of a dielectric material over the die and patterning the dielectric layer. The patterning the dielectric layer includes forming a supporting pad area and forming a conductive channel area. A portion of the conductive channel area passes at least partially through the supporting pad area. At least one dielectric region interpose the portion of the conductive channel area and the supporting pad area. The forming the connective further includes filling the supporting pad area and the conductive channel area with a conductive material. The supporting pad area of the conductive material forms a supporting pad. The conductive channel area of the conductive material forms a conductive channel.

Claims (55)

1. A method, comprising:

providing a die, wherein the die comprises a substrate and a bonding pad over the substrate;

forming a connective layer over the die, wherein the forming the connective layer comprises:

depositing a dielectric layer of a dielectric material over the die;

patterning the dielectric layer, wherein the patterning the dielectric layer comprises:

forming a supporting pad area; and

forming a conductive channel area, wherein a portion of the conductive channel area passes at least partially through the supporting pad area, wherein at least one dielectric region interpose the portion of the conductive channel area and the supporting pad area; and

filling the supporting pad area and the conductive channel area with a conductive material, wherein the supporting pad area of the conductive material forms a supporting pad, and wherein the conductive channel area of the conductive material forms a conductive channel; and

forming a landing pad over the connective layer.

2. The method of claim 1 , further comprising:

mounting a bump structure above the landing pad.

3. The method of claim 2 , wherein the bump structure includes a bump contact region in direct physical contact with a top surface of the landing pad.

4. The method of claim 2 , wherein a center of the bump structure substantially aligns with the center of the supporting pad.

5. The method of claim 2 , wherein the mounting the bump structure includes:

forming an under-bump-metallization (UBM) layer disposed above the landing pad.

6. The method of claim 1 , further comprising:

prior to forming the landing pad, forming an intermediate layer over the connective layer;

wherein the landing pad is disposed over the intermediate layer.

7. The method of claim 6 , wherein the landing pad is electrically coupled to the conductive channel in the connective layer through a conductive via in the intermediate layer.

8. A method, comprising:

providing a die including a multilayer interconnect (MLI) structure, wherein the MLI structure includes a first conductive component and a second conductive component;

forming a first connective layer disposed over the die, wherein the forming the first connective layer includes:

depositing a dielectric layer of a dielectric material over the die;

patterning the dielectric layer, wherein the patterning the dielectric layer comprises:

forming a supporting pad area; and

forming a continuous conductive planar path area, wherein a portion of the continuous conductive planar path area passes at least partially through the supporting pad area, wherein at least one dielectric region interpose the portion of the continuous conductive planar path area and the supporting pad area; and

filling the supporting pad area and the continuous conductive planar path area with a conductive material, wherein the supporting pad area of the conductive material forms a supporting pad, and wherein the continuous conductive planar path area of the conductive material forms a continuous conductive planar path;

wherein the supporting pad is electrically connected to the first conductive component of the MLI structure, and

wherein the continuous conductive planar path is electrically connected to the second conductive component of the MLI structure.

9. The method of claim 8 , further comprising:

forming a second connective layer disposed over the first connective layer, wherein the second connective layer includes a landing pad.

10. The method of claim 9 , further comprising:

prior to the forming the second connective layer, forming an intermediate layer formed over the first connective layer;

wherein the second connective layer is disposed over the intermediate layer.

11. The method of claim 10 , further comprising:

forming a bump structure disposed above the landing pad, wherein the bump structure includes a conductive bump,

wherein the bump structure includes a bump contact region in direct physical contact with a top surface of the landing pad.

12. The method of claim 11 , wherein the bump contact region has an area of a smaller size than a top surface of the supporting pad.

13. The method of claim 11 , wherein a first center of the bump contact region is substantially aligned with a second center of the supporting pad.

14. The method of claim 11 , further comprising:

providing a second die;

wherein the landing pad is electrically connected to the second die using a Through-Substrate-Via (TSV) structure.

15. The method of claim 11 , wherein the landing pad is electrically connected to the continuous conductive planar path by a conductive via in the intermediate layer.

16. The method of claim 11 , wherein the landing pad is electrically connected to the supporting pad by a conductive via in the intermediate layer.

17. The method of claim 11 , wherein the MLI structure includes a third conductive component, and wherein the landing pad is electrically connected to the third conductive component.

18. A method, comprising:

providing a substrate including a first device and a second device;

forming a first conductive pad disposed over the substrate and electrically connected to the first device;

forming a second conductive pad disposed over the substrate and electrically connected to the second device;

forming a passivation layer disposed over the first conductive pad and the second conductive pad, wherein a first portion of the first conductive pad is exposed in a first opening of the passivation layer, and a second portion of the second conductive pad is exposed in a second opening of the passivation layer;

forming a connective layer disposed over the passivation layer, wherein the connective layer includes a supporting pad electrically connected to the first device through the first portion of the first conductive pad, wherein the supporting pad has an opening extending from an edge of the supporting pad to a point within the supporting pad, and wherein the opening includes

a continuous conductive planar path electrically connected to the second device through the second portion of the second conductive pad; and

at least one dielectric component interposed between the continuous conductive planar path and the supporting pad.

19. The method of claim 18 , wherein the point within the supporting pad is a second edge of the supporting pad.

20. The method of claim 18 , wherein the opening extends to a second point within the supporting pad to form an opening branch.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2017
From: CHIU, CHIEN-CHIA; CHIU, MING-YEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 044121/0097 →
Continuity (2)
Division 14755889 · Jun 30, 2015
Related Publication 20180068968A1 · Mar 8, 2018