Validate written data

1. A device, comprising:

a memory; and

a processor to:

receive, from a source, first data and a first error detection code related to the first data;

write the first data to the memory to store written first data in the memory;

validate that the first data is written correctly to the memory, the validating comprising reading the written first data from the memory to produce read data, and performing a comparison that comprises:

comparing a second error detection code generated based on the read data with the first error detection code received from the source; and

generate an alert if the validating determines that the first data written to the memory is incorrect.

2. The device of claim 1 , wherein the processor is to further:

before writing the first data to the memory, validate if the first data is correct based on the first error detection code received from the source,

wherein the writing of the first data to the memory is in response to validating that the first data is correct.

3. The device of claim 2 , wherein the processor is to:

generate a third error detection code based on the first data, before the first data is written to the memory; and

compare the third error detection code to the first error detection code, to validate if the first data is correct.

4. The device of claim 3 , wherein the processor is to:

indicate that the first data is incorrect if the third error detection code does not match the first error detection code; and

indicate that the first data is correct if the third error detection code matches the first error detection code.

5. The device of claim 1 , wherein the processor is to:

generate the second error detection code based on the read data; and

indicate that the first data written to the memory is incorrect if the second error detection code does not match the first error detection code.

6. The device of claim 1 , further comprising

a controller to generate the first error detection code based on input data before sending the input data to the processor, the input data received on the first data by the processor, and

the controller is to receive the alert and to retransmit the input data to the processor in response to the alert.

7. The device of claim 1 , further comprising:

a double data rate (DDR) memory interface to receive the first data,

wherein the first error detection code is a cyclic redundancy check (CRC), and the memory is a dynamic random-access memory (DRAM).

8. A method, comprising:

receiving, by a device from a source, first data to be written to a memory and a first detection code related to the first data;

writing, by the device, the first data to the memory to store written first data in the memory;

after the writing, reading, by the device, the written first data from the memory to produce read data;

generating, by the device, a second error detection code based on the read data;

comparing, by the device, the second error detection code to the first error detection code received from the source to validate that the first data is correctly written to the memory; and

generating, by the device, an alert in response to the first error detection code not matching the second error detection code.

9. The method of claim 8 , further comprising:

before the writing, generating a third error detection code based on the first data;

comparing the third error detection code to the first error detection code; and

generating an alert in response to the first error detection not matching the third detection code.

10. The method of claim 8 , wherein the source is a controller, the method further comprising:

sending, by the device to the controller, the alert; and

receiving, by the device from the controller, a retransmission of the first data responsive to the alert sent to the controller.

11. A non-transitory computer-readable storage medium storing instructions that upon execution cause a device to:

receive, from a source, a first error detection code related to first data to be written to a memory;

write the first data to the memory to store written first data in the memory;

validate that the first data written to the memory is correct, the validating comprising reading the written first data from the memory to produce read data, and performing a comparison that comprises:

comparing a second error detection code generated based on the read data with the first error detection code received from the source; and

generate an error if the validating indicates that the first data is incorrectly written to the memory.

12. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions upon execution cause the device to:

generate the second error detection code based on the read data.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the instructions upon execution cause the device to:

generate a third error detection code based on the first data; and

validate the first data based on a comparison of the first error detection code to the third error detection code, before the first data is written to the memory.

14. The method of claim 13 , wherein the writing of the first data to the memory is in response to the third error detection code matching the first error detection code.

15. The method of claim 9 , further comprising:

receiving second data to be written to the memory and a fourth error detection code related to the second data;

generating a fifth error detection code based on the second data;

comparing the fifth error detection code to the fourth error detection code; and

declining to write the second data to the memory in response to the fifth error detection code not matching the fourth error detection code.

16. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions upon execution cause the device to:

send the error to a controller that sent the first data to the device.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the validating is performed without involvement of the controller.

18. The non-transitory computer-readable storage medium of claim 11 , wherein the source is a controller, and wherein the instructions upon execution cause the device to:

send, to the controller, the alert; and

receive, from the controller, a retransmission of the first data responsive to the alert sent to the controller.