Memory access validation for input/output operations using an interposer
Memory access validation for input/output operations using an interposer is described. In one or more implementations, an interposer is disposed logically between an input/output device and a memory. The interposer receives a plurality of requests from the input/output device to access the memory non-sequentially in association with an input/output operation. Responsive to each request, the interposer updates an accumulated error code using error-detection logic. Based upon the accumulated error code, the interposer outputs an I/O validity indicator.
1 . A device comprising:
an interposer disposed logically between an input/output device and a memory to:
receive a plurality of requests from the input/output device to access the memory non-sequentially in association with an input/output operation;
responsive to each request of the plurality of requests, incrementally update an accumulated error code based at least in part on an indication of which particular bytes of the memory are requested in each request of the plurality of requests, wherein the accumulated error code is updated incrementally with each request based on at least one error detection algorithm; and
output an input/output validity indicator for the input/output operation based on the accumulated error code.
2 . The device of claim 1 , wherein the interposer is further configured to validate the input/output operation based on the accumulated error code.
3 . The device of claim 1 , wherein the plurality of requests is received from a direct memory access engine of the input/output device.
4 . The device of claim 1 , wherein the input/output device is a non-volatile memory express (NVMe) device and the interposer is an NVMe interposer.
5 . The device of claim 1 , wherein error-detection logic of the interposer performs incremental cyclic redundancy code (CRC) calculations associated with the at least one error detection algorithm for each request on a per-request basis as a request is received to update the accumulated error code.
6 . The device of claim 5 , wherein the error-detection logic comprises a linear feedback shift register (LFSR) for performing the incremental cyclic redundancy code (CRC) calculations.
7 . The device of claim 1 , wherein the interposer is further configured to validate the input/output operation based on the accumulated error code and an input/output level error code.
8 . The device of claim 7 , wherein the accumulated error code and the input/output level error code are cyclic redundancy codes (CRCs).
9 . The device of claim 7 , wherein the interposer stores both the accumulated error code and the input/output level error code without storing a virtual bit vector having a number of bits which corresponds to a number of bytes of the input/output operation.
10 . The device of claim 7 , wherein:
error-detection logic of the interposer updates the accumulated error code for a request according to the at least one error detection algorithm based on a number of bytes of memory requested for access by the request and the indication of which particular bytes of the memory are requested; and
the error-detection logic updates the input/output level error code for the request based on the number of bytes of memory requested.
11 . The device of claim 10 , wherein the error-detection logic updates the input/output level error code for the request based on the number of bytes of memory requested by the request and agnostic to which particular bytes of the memory are requested.
12 . The device of claim 1 , wherein the interposer is further configured to translate the plurality of requests to produce a plurality of translated requests for accessing respective portions of the memory.
13 . The device of claim 12 , wherein the plurality of translated requests are formatted according to a different protocol than the plurality of requests.
14 . The device of claim 1 , wherein the indication of which particular bytes of the memory are requested indicates an offset and a number of bytes accessed by the request.
15 . The device of claim 1 , wherein the input/output device is configured to perform the input/output operation again in response to the input/output validity indicator indicating that the input/output operation is invalid.
16 . A system comprising:
a memory;
an input/output device to generate a plurality of requests to access the memory non-sequentially in association with an input/output operation; and
an interposer disposed logically between the memory and the input/output device, the interposer having error-detection logic to incrementally update an accumulated error code based at least in part on an indication of which particular bytes of the memory are requested in each request of the plurality of requests and output an input/output validity indicator based on the accumulated error code, wherein the accumulated error code is updated incrementally with each request of the plurality of requests based on at least one error detection algorithm.
17 . The system of claim 16 , wherein the interposer is further configured to use the error-detection logic to update an input/output level error code based on each request, the interposer updating the input/output level error code based on different input information than the accumulated error code.
18 . The system of claim 17 , wherein the interposer is further configured to validate the input/output operation based on both the accumulated error code and the input/output level error code.
19 . The system of claim 17 , wherein the interposer is further configured to validate the input/output operation based on whether the accumulated error code and the input/output level error code are equal.
20 . A method comprising:
receiving, by an interposer and from an input/output device, a plurality of requests to access memory non-sequentially in association with an input/output operation;
responsive to each request of the plurality of requests, incrementally updating an accumulated error code based at least in part on an indication of which particular bytes of the memory are requested in each request of the plurality of requests, wherein the accumulated error code is updated incrementally with each request based on at least one error detection algorithm; and
outputting, by the interposer, an input/output validity indicator based on the accumulated error code.