Comparator for double ramp analog to digital converter
Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.
1. A method, comprising:
disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator;
adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator; and
disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator,
wherein the first auto-zero switch is coupled between a gate of the reference voltage input and a node between a PMOS transistor and a cascode device, wherein the reference voltage input is an NMOS transistor, and wherein the cascode device is coupled between the reference voltage input and the PMOS transistor, and
wherein the second auto-zero switch is coupled between a gate of the bitline input and a node between a PMOS transistor and a cascode device, wherein the bitline input is an NMOS transistor, and wherein the cascode device is coupled between the bitline input and the PMOS transistor.
2. The method of claim 1 , wherein adjusting the auto-zero offset voltage of the ramp voltage provided to the reference voltage input of the comparator comprises:
increasing the auto-zero offset voltage of the ramp voltage in response to the comparator having low analog gain.
3. The method of claim 2 , wherein increasing the auto-zero offset voltage of the ramp voltage in response to the comparator having low analog gain comprises:
increasing the auto-zero offset voltage of the ramp voltage by an amount proportional to a threshold voltage of NMOS input transistors of the comparator, wherein the NMOS input transistors are the reference voltage and bitline inputs.
4. The method of claim 1 , wherein adjusting the auto-zero offset voltage of the ramp voltage provided to the reference voltage input of the comparator comprises:
decreasing the auto-zero offset voltage of the ramp voltage in response to the comparator having high analog gain.
5. The method of claim 4 , further comprising:
enabling cascode devices of the comparator, wherein the cascode devices are coupled between the reference voltage and bitline inputs and a pair of PMOS transistors.
6. The method of claim 4 , wherein decreasing the auto-zero offset voltage of the ramp voltage in response to the comparator having high analog gain comprises:
decreasing the auto-zero offset voltage of the ramp voltage to cause a drain to source voltage of NMOS input transistors of the comparator to increase, wherein the NMOS input transistors are the reference voltage and bitline inputs.