Imaging device, operation method thereof, and electronic device
View Patent ↗An imaging device with low power consumption is provided. A pixel includes a first circuit and a second circuit. The first circuit can generate imaging data and retain difference data that is a difference between the imaging data and data obtained in an initial frame. The second circuit includes a circuit that compares the difference data and a voltage range set arbitrarily. The second circuit supplies a reading signal based on the comparison result. With the use of the structure, reading from the pixel is not performed when it is determined that the difference data is within the set voltage range and reading from the pixel can be performed when it is determined that the difference data is outside the voltage range.
1. An imaging device comprising:
a plurality of pixels, one of the plurality of pixels comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer; and
a fourth layer over the third layer,
wherein the first layer comprises a first circuit,
wherein the first circuit comprises:
a first transistor;
a second transistor; and
a third transistor,
wherein the second layer comprises a second circuit,
wherein the second circuit comprises:
a fourth transistor; and
a fifth transistor,
wherein the third layer comprises a photoelectric conversion device,
wherein the fourth layer comprises:
a light-blocking layer;
an optical conversion layer; and
a microlens array,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and
wherein one of a source and a drain of the fifth transistor is electrically connected to one electrode of the photoelectric conversion device.
2. An imaging device comprising:
a plurality of pixels, one of the plurality of pixels comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer; and
a fourth layer over the third layer,
wherein the first layer comprises a first circuit,
wherein the first circuit comprises:
a first transistor;
a second transistor; and
a third transistor,
wherein the second layer comprises a second circuit,
wherein the second circuit comprises:
a fourth transistor; and
a fifth transistor,
wherein the third layer comprises a photoelectric conversion device,
wherein the fourth layer comprises a microlens array,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor, and
wherein one of a source and a drain of the fifth transistor is electrically connected to one electrode of the photoelectric conversion device.
3. An imaging device comprising:
a plurality of pixels, one of the plurality of pixels comprising:
a first layer;
a second layer over the first layer;
a third layer over the second layer; and
a fourth layer over the third layer,
wherein the first layer comprises a first circuit,
wherein the first circuit comprises:
a first transistor;
a second transistor; and
a third transistor,
wherein the second layer comprises a second circuit,
wherein the second circuit comprises:
a fourth transistor; and
a fifth transistor,
wherein the third layer comprises a photoelectric conversion device,
wherein the fourth layer comprises a microlens array,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one electrode of the photoelectric conversion device,
wherein the first transistor comprises silicon in a first channel formation region,
wherein the second transistor comprises silicon in a second channel formation region,
wherein the third transistor comprises silicon in a third channel formation region,
wherein the fourth transistor comprises a metal oxide in a fourth channel formation region, and
wherein the fifth transistor comprises a metal oxide in a fifth channel formation region.
4. The imaging device according to claim 1 ,
wherein the first transistor comprises silicon in a first channel formation region,
wherein the second transistor comprises silicon in a second channel formation region,
wherein the third transistor comprises silicon in a third channel formation region,
wherein the fourth transistor comprises a metal oxide in a fourth channel formation region, and
wherein the fifth transistor comprises a metal oxide in a fifth channel formation region.
5. The imaging device according to claim 1 ,
wherein, in a cross-sectional view, one of the first transistor, the second transistor, and the third transistor overlaps with one of the fourth transistor and the fifth transistor, and
wherein, in the cross-sectional view, the one of the first transistor, the second transistor, and the third transistor overlaps with the photoelectric conversion device and the microlens array.
6. The imaging device according to claim 2 ,
wherein, in a cross-sectional view, one of the first transistor, the second transistor, and the third transistor overlaps with one of the fourth transistor and the fifth transistor, and
wherein, in the cross-sectional view, the one of the first transistor, the second transistor, and the third transistor overlaps with the photoelectric conversion device and the microlens array.
7. The imaging device according to claim 3 ,
wherein, in a cross-sectional view, one of the first transistor, the second transistor, and the third transistor overlaps with one of the fourth transistor and the fifth transistor, and
wherein, in the cross-sectional view, the one of the first transistor, the second transistor, and the third transistor overlaps with the photoelectric conversion device and the microlens array.
8. The imaging device according to claim 1 ,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of a sixth transistor, a gate of a seventh transistor, and one electrode of a first capacitor, and
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor.
9. The imaging device according to claim 2 ,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of a sixth transistor, a gate of a seventh transistor, and one electrode of a first capacitor, and
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor.
10. The imaging device according to claim 3 ,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of a sixth transistor, a gate of a seventh transistor, and one electrode of a first capacitor, and
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor.
11. The imaging device according to claim 1 ,
wherein a gate of the first transistor is electrically connected to a gate of the second transistor, and
wherein the fourth transistor is not electrically connected to the fifth transistor.
12. The imaging device according to claim 2 ,
wherein a gate of the first transistor is electrically connected to a gate of the second transistor, and
wherein the fourth transistor is not electrically connected to the fifth transistor.
13. The imaging device according to claim 3 ,
wherein a gate of the first transistor is electrically connected to a gate of the second transistor, and
wherein the fourth transistor is not electrically connected to the fifth transistor.
14. The imaging device according to claim 1 ,
wherein the gate of the fourth transistor does not overlap with a gate of the first transistor, a gate of the second transistor, and the gate of the third transistor, and
wherein the fourth transistor is not electrically connected to the fifth transistor.
15. The imaging device according to claim 2 ,
wherein the gate of the fourth transistor does not overlap with a gate of the first transistor, a gate of the second transistor, and the gate of the third transistor, and
wherein the fourth transistor is not electrically connected to the fifth transistor.
16. The imaging device according to claim 3 ,
wherein the gate of the fourth transistor does not overlap with a gate of the first transistor, a gate of the second transistor, and the gate of the third transistor, and
wherein the fourth transistor is not electrically connected to the fifth transistor.
17. The imaging device according to claim 2 ,
wherein the first transistor is provided in an inverter circuit, and
wherein the second transistor is provided in an inverter circuit.
18. The imaging device according to claim 3 ,
wherein the first transistor is provided in an inverter circuit, and
wherein the second transistor is provided in an inverter circuit.