IP Library › Granted Patent US 10,090,298
Granted Patent B2
US 10,090,298 · App. 15/447,800 · Granted Oct 2, 2018

Integrated packaging structure

Inventors: Chien-Chung Chen (New Taipei, TW); Sen Mao (New Taipei, TW); Hsin-Liang Lin (New Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR CO., LTD.
H01L27/088H01L23/4952H01L23/49503H01L23/49562H01L23/49586H01L29/0634H01L29/41725
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,090,298
App. No.
15/447,800
Granted
Oct 2, 2018
Kind
B2
Abstract

An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.

Claims (22)

1. An integrated packaging structure, comprising:

an integrated circuit (IC) unit, comprising:

a main body, having a first source region, a second source region, a first gate region, a second gate region, a first setting region, and a second setting region, which are separated from each other;

a first metal-oxide-semiconductor field-effect transistor (MOSFET) die, located on the first setting region, having a first upper layer, and comprising:

at least one first source electrode pad, exposed through the first upper layer; and

two first gate electrode pads, spaced apart from the at least one first source electrode pad, and exposed through the first upper layer;

a second MOSFET die, located on the second setting region, having a second upper layer, and comprising:

at least one second source electrode pad, exposed through the second upper layer; and

two second gate electrode pads, spaced apart from the at least one second source electrode pad, and exposed through the second upper layer;

at least one first source connection element, connected to the at least one first source electrode pad and the first source region;

at least one second source connection element, connected to the at least one second source electrode pad and the second source region;

at least one first gate connection element, connected to the two first gate electrode pads and the first gate region; and

at least one second gate connection element, connected to the two second gate electrode pads and the second gate region; and

a packaging body, at least partially covering the IC unit;

wherein the first MOSFET die and the second MOSFET die are super junction MOSFET dies;

wherein the first source region includes at least one first source pin, the second source region includes at least one second source pin, the first gate region includes at least one first gate pin, the second gate region includes at least one second gate pin, and the at least one first gate pin, the at least one first source pin, the at least one second source pin, and the at least one second gate pin are arranged along a direction in a serial;

wherein the first gate electrode pads are arranged at corresponding corners of the first MOSFET die and the second electrode pads are arranged at corresponding corners of the second MOSFET die.

2. The integrated packaging structure of claim 1 , wherein the at least first one source connection element and the at least one second source connection element are one-piece metal clips.

3. The integrated packaging structure of claim 1 , wherein the at least first source connection element and the at least one second source connection element are at least one conductive wire.

4. The integrated packaging structure of claim 1 , wherein the at least first gate connection element and the at least one second gate connection element are at least one conductive wire.

5. The integrated packaging structure of claim 1 , wherein the first source region is adjacent to the second source region.

6. The integrated packaging structure of claim 1 , wherein a distance is left between the first setting region and the second setting region, and the distance is greater than 1.805 mm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2017
From: CHEN, CHIEN-CHUNG; MAO, SEN; LIN, HSIN-LIANG
To: TAIWAN SEMICONDUCTOR CO., LTD.
Reel/Frame 041453/0372 →
Priority Claims (1)
TW 106201068 U · Jan 20, 2017 · national
Continuity (1)
Related Publication 20180211953A1 · Jul 26, 2018