Semiconductor device and method of fabricating the same
A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.
1. A semiconductor device, comprising:
first and second active patterns protruding upward from a substrate;
a gate electrode crossing the first and second active patterns, the gate electrode extending in a first direction;
a first source/drain region on the first active pattern and on at least one side of the gate electrode, the first source/drain region having a first bottom surface in contact with a first top surface of the first active pattern; and
a second source/drain region on the second active pattern and on at least one side of the gate electrode, the second source/drain region having a conductivity type different from that of the first source/drain region, the second source/drain region having a second bottom surface in contact with a second top surface of the second active pattern and at a lower level than the first bottom surface,
wherein the first top surface of the first active pattern has a first width in the first direction,
the second top surface of the second active pattern has a second width greater than the first width in the first direction, and
a top surface of an interconnecting recess region between the first source/drain region and the second source/drain region is lower than a top surface of a first recess region adjacent to the first source/drain region or a top surface of a second recess region adjacent to the second source/drain region.
2. The device of claim 1 , wherein
the first active pattern and the first source/drain region constitute an NMOSFET; and
the second active pattern and the second source/drain region constitute a PMOSFET.
3. The device of claim 1 , wherein
the first active pattern includes a first channel region and the second active pattern includes a second channel region when viewed in a plan view;
the gate electrode overlaps the first and second channel regions; and
a surface area directly contacting the second channel region and the second source/drain region is greater than a surface area directly contacting the first channel region and the first source/drain region.
4. The device of claim 3 , wherein the first and second channel regions have top surfaces at a same level.
5. The device of claim 1 , wherein
the first source/drain region includes a material having a first lattice constant equal to or smaller than that of the substrate; and
the second source/drain region includes a material having a second lattice constant greater than that of the substrate.
6. The device of claim 1 , wherein a maximum width of the first source/drain region in the first direction is a third width and a maximum width of the second source/drain region in the first direction is a fourth width different from the third width.
7. The device of claim 1 , further comprising:
a device isolation pattern on the substrate and filling a gap region between the first and second active patterns, the device isolation pattern including,
a first portion having a top surface, the gate electrode overlapping the first portion in a plan view, and
a second portion on at least one side of the gate electrode, the second portion defining the interconnecting recess region having a bottom surface lower than the top surface of the first portion.
8. The device of claim 7 , wherein the bottom surface of the interconnecting recess region is lower than the first and second bottom surfaces of the first and second source/drain regions.
9. The device of claim 7 , further comprising:
an etch stop layer covering the first and second source/drain regions and the device isolation pattern, the etch stop layer directly covering an inner surface of the interconnecting recess region.
10. The device of claim 1 , further comprising:
gate spacers on opposite sides of the gate electrode; and
a gate insulating pattern between the gate electrode and the first and second active patterns, and between the gate electrode and the gate spacers.
11. A semiconductor device, comprising:
a first MOSFET structure including,
at least one first active pattern protruding upward from a substrate,
at least one first source/drain region having a first bottom surface contacting a first top surface of the first active pattern;
a second MOSFET structure including,
at least one second active pattern protruding upward from the substrate,
at least one second source/drain region having a second bottom surface contacting a second top surface of the second active pattern and at a lower level than the first bottom surface, the second source/drain region having a different shape than the first source/drain region,
wherein the first top surface of the first active pattern has a first width,
the second top surface of the second active pattern has a second width greater than the first width, and
a top surface of an interconnecting recess region between the first source/drain region and the second source/drain region is lower than a top surface of a first recess region adjacent to the first source/drain region or a top surface of a second recess region adjacent to the second source/drain region.
12. The device of claim 11 , wherein
the first source/drain region includes a material having a first lattice constant equal to or smaller than that of the substrate; and
the second source/drain region includes a material having a second lattice constant greater than that of the substrate.
13. The device of claim 11 , wherein a maximum width of the first source/drain region is a third width and a maximum width of the second source/drain region is a fourth width different from the third width.
14. The device of claim 11 , wherein
the at least one first active pattern is a pair of first active patterns and a distance between the pair of first active patterns is a first length;
the at least one second active pattern is a pair of second active patterns and a distance between the pair of second active patterns is a second length longer than the first length; and
a distance between the pair of first active patterns and the pair of second active patterns is a third length longer than the second length.
15. A semiconductor device, comprising:
first and second active patterns protruding upward from a substrate;
a gate electrode crossing the first and second active patterns, the gate electrode extending in a first direction;
a device isolation layer on the substrate and covering lower sidewalls of the first and second active patterns;
a first source/drain region on the first active pattern and on at least one side of the gate electrode, the first source/drain region having a first bottom surface in contact with a first top surface of the first active pattern;
a second source/drain region on the second active pattern and on at least one side of the gate electrode, the second source/drain region having a conductivity type different from that of the first source/drain region, the second source/drain region having a second bottom surface in contact with a second top surface of the second active pattern and at a lower level than the first bottom surface; and
a first air gap between the first source/drain region and the device isolation layer,
wherein the first top surface of the first active pattern has a first width in the first direction, and
the second top surface of the second active pattern has a second width greater than the first width in the first direction.
16. The device of claim 15 , further comprising an etch stop layer covering the first and second source/drain regions and the device isolation layer,
wherein the first air gap is separated from the etch stop layer.
17. The device of claim 15 , further comprising a second air gap between the second source/drain region and the device isolation layer,
wherein the second air gap is deeper than the first air gap.
18. The device of claim 15 , wherein
the first active pattern and the first source/drain region constitute an NMOSFET; and
the second active pattern and the second source/drain region constitute a PMOSFET.
19. The device of claim 15 , wherein
the first source/drain region includes a material having a first lattice constant equal to or smaller than that of the substrate; and
the second source/drain region includes a material having a second lattice constant greater than that of the substrate.
20. The device of claim 15 , wherein a maximum width of the first source/drain region in the first direction is a third width and a maximum width of the second source/drain region in the first direction is a fourth width different from the third width.