IP Library Granted Patent US 12,622,015
Granted Patent B2
US 12,622,015 · App. 18/595,696 · Granted May 5, 2026

Semiconductor devices having variously-shaped source/drain patterns

Inventors: Hyun-Kwan Yu (Suwon-si, KR); Min-Hee Choi (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D30/6219H01L21/76224H10D84/0133H10D84/0158H10D84/038H10D84/834
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Quick Facts
Patent No.
US 12,622,015
App. No.
18/595,696
Granted
May 5, 2026
Kind
B2
Abstract

A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

Claims (62)

1 . A method of fabricating a semiconductor device, the method comprising:

patterning a substrate to form a first active pattern and a second active pattern, the first active pattern comprising a first sidewall that faces the second active pattern and a second sidewall opposite from the first sidewall;

forming a device isolation layer comprising an outer segment and an intermediate segment, the outer segment on the second sidewall, the intermediate segment between the first and second active patterns;

forming a sacrificial pattern that crosses the first and second active patterns;

forming a mask pattern on the sacrificial pattern;

forming a gate spacer on a sidewall of the sacrificial pattern;

etching the first and second active patterns, the outer segment, and the intermediate segment using the mask pattern and the gate spacer as an etch mask; and

forming a source/drain pattern on the first and second active patterns,

wherein an uppermost level of the etched outer segment is lower than a lowermost level of a top surface of the etched intermediate segment.

2 . The method of claim 1 , wherein the etching of the outer segment comprises exposing the second sidewall of the first active pattern.

3 . The method of claim 1 , wherein the source/drain pattern comprises:

a first part in contact with the first active pattern;

a second part in contact with the second active pattern; and

a third part in contact with the first active pattern and the outer segment,

wherein the first, second, and third parts of the source/drain pattern are merged with each other, and

wherein a lowermost level of the third part of the source/drain pattern is closer to the substrate than the lowermost level of the top surface of the etched intermediate segment.

4 . The method of claim 3 , wherein a void is between the first and second parts of the source/drain pattern.

5 . The method of claim 3 , wherein the first part of the source/drain pattern is in contact with a top surface of the first active pattern, and

wherein the third part of the source/drain pattern is in contact with the second sidewall of the first active pattern.

6 . The method of claim 3 , wherein the third part of the source/drain pattern comprises a rounded outer surface.

7 . The method of claim 1 , wherein the first sidewall of the first active pattern is spaced apart from the source/drain pattern.

8 . A method of fabricating a semiconductor device, comprising:

patterning a substrate to form a first active pattern and a second active pattern, the first active pattern comprising a first sidewall that faces the second active pattern and a second sidewall opposite from the first sidewall;

forming a device isolation layer comprising an outer segment and an intermediate segment, the outer segment covering a lower portion of the second sidewall of the first active pattern and the intermediate segment covering a lower portion of the first sidewall of the first active pattern;

forming a sacrificial pattern that crosses the first and second active patterns;

forming a mask pattern on the sacrificial pattern;

forming a gate spacer on a sidewall of the sacrificial pattern;

etching the first and second active patterns, the outer segment, and the intermediate segment using the mask pattern and the gate spacer as an etch mask; and

forming a source/drain pattern on the first and second active patterns,

wherein a height of a portion of the lower portion of the second sidewall of the first active pattern that is exposed by etching the outer segment is greater than a height of a portion of the lower portion of the first sidewall of the first active pattern that is exposed by etching the intermediate segment,

wherein the source/drain pattern comprises:

a first part on a top surface of the first active pattern;

a second part on a top surface of the second active pattern; and

a third part on the portion of the lower portion of the second sidewall of the first active pattern, and

wherein a lowermost level of the third part of the source/drain pattern is closer to the substrate than a lowermost level of a top surface of the etched intermediate segment is to the substrate.

9 . The method of claim 8 , wherein the forming of the source/drain pattern comprises performing an epitaxial growth process using the portion of the lower portion of the second sidewall as a seed layer.

10 . The method of claim 8 , wherein the first, second, and third parts of the source/drain pattern are merged with each other, and

wherein a top surface of the first part of the source/drain pattern and a top surface of the second part of the source/drain pattern are coplanar.

11 . The method of claim 8 , wherein the lowermost level of the third part of the source/drain pattern is closer to a surface of the substrate than a lowermost level of the portion of the lower portion of the second sidewall of the first active pattern is to the substrate.

12 . The method of claim 8 , wherein a void is between the first and second parts of the source/drain pattern.

13 . The method of claim 8 , wherein the first part of the source/drain pattern is in contact with a top surface of the first active pattern, and

wherein the third part of the source/drain pattern is in contact with the second sidewall of the first active pattern.

14 . The method of claim 8 , wherein the third part of the source/drain pattern comprises a rounded outer surface.

15 . The method of claim 8 , wherein the etching of the outer segment comprises exposing the second sidewall of the first active pattern.

16 . The method of claim 8 , wherein the first sidewall of the first active pattern is spaced apart from the source/drain pattern.

17 . A method of fabricating a semiconductor device, comprising:

patterning a substrate to form a first active pattern and a second active pattern, the first active pattern comprising a first sidewall that faces the second active pattern and a second sidewall opposite from the first sidewall;

forming a device isolation layer comprising an outer segment and an intermediate segment, the outer segment covering a lower portion of the second sidewall of the first active pattern and the intermediate segment covering a lower portion of the first sidewall of the first active pattern;

forming a sacrificial pattern that crosses the first and second active patterns;

forming a mask pattern on the sacrificial pattern;

forming a gate spacer on a sidewall of the sacrificial pattern;

etching the first and second active patterns, the outer segment, and the intermediate segment using the mask pattern and the gate spacer as an etch mask; and

forming a source/drain pattern on the first and second active patterns, wherein a height of a portion of the lower portion of the second sidewall of the first active pattern that is exposed by etching the outer segment is greater than a height of a portion of the lower portion of the first sidewall of the first active pattern that is exposed by etching the intermediate segment,

wherein an uppermost level of the etched outer segment is closer to the substrate than a lowermost level of a top surface of the etched intermediate segment is to the substrate.

18 . The method of claim 17 , wherein the etching of the outer segment comprises exposing the second sidewall of the first active pattern.

19 . The method of claim 17 , wherein the first sidewall of the first active pattern is spaced apart from the source/drain pattern.

20 . The method of claim 17 , wherein the source/drain pattern comprises:

a first part in contact with the first active pattern;

a second part in contact with the second active pattern; and

a third part in contact with the first active pattern and the outer segment,

wherein the first, second, and third parts of the source/drain pattern are merged with each other, and

wherein a lowermost level of the third part of the source/drain pattern is closer to the substrate than the lowermost level of the top surface of the etched intermediate segment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2026
From: YU, HYUN-KWAN; CHOI, MIN-HEE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 074293/0178 →
Priority Claims (1)
KR 10-2018-0067354 · Jun 12, 2018 · national
Continuity (4)
Continuation 18196533 · May 12, 2023
Continuation 17131977 · Dec 23, 2020
Continuation 16252919 · Jan 21, 2019
Related Publication 20240204070A1 · Jun 20, 2024
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