Semiconductor device

1. A semiconductor device comprising:

an active pattern having sidewalls defined by a device isolation pattern on a substrate, the active pattern having an upper portion protruding from a top surface of the device isolation pattern;

a liner insulating layer on the sidewalls of the active pattern;

a gate structure on the active pattern; and

source/drain regions at both sides of the gate structure,

wherein the liner insulating layer comprises:

a first liner insulating layer extending between the active pattern and the device isolation pattern; and

a second liner insulating layer having a first portion between the first liner insulating layer and the device isolation pattern, and a second portion protruding above the top surface of the device isolation pattern and having a top surface higher than a top surface of the first liner insulating layer, and

wherein each of the source/drain regions comprises:

a first portion defined by the second liner insulating layer; and

a second portion protruding upward above the second liner insulating layer and formed above a topmost surface of the first liner insulating layer.

2. The semiconductor device of claim 1 ,

wherein the first portion of each of the source/drain regions is in contact with a sidewall of the second portion of the second liner insulating layer.

3. The semiconductor device of claim 1 , wherein a top surface of the first liner insulating layer overlapping with the gate structure is at a substantially same level as a top surface of the second liner insulating layer overlapping with the gate structure.

4. The semiconductor device of claim 1 , further comprising:

a first spacer provided on the second liner insulating layer, the first spacer being in contact with the top surface of the device isolation pattern.

5. The semiconductor device of claim 4 , wherein the gate structure comprises:

a gate electrode; and

a second spacer provided on a sidewall of the gate electrode, and

wherein the first spacer is formed of the same material as the second spacer.

6. The semiconductor device of claim 1 , wherein the active pattern comprises: a first portion overlapping with the gate structure; and second portions overlapping with the source/drain regions,

wherein top surfaces of the second portions of the active pattern are lower than a top surface of the first portion of the active pattern,

wherein the second portions of the active pattern are inserted in the first portions of the source/drain regions, respectively, and

wherein an upper portion of each of the second portions of the active pattern has a rounded surface.

7. The semiconductor device of claim 6 , wherein the first portions of the source/drain regions extend onto sidewalls of the second portions of the active pattern.

8. The semiconductor device of claim 1 , wherein a topmost surface of the first liner insulating layer is at a substantially same level as or a lower level than the top surface of the device isolation pattern.

9. The semiconductor device of claim 1 , wherein the gate structure extends in one direction, and

wherein, for each of the source/drain regions, a width in the one direction of the first portion of the source/drain region is smaller than a width in the one direction of the second portion of the source/drain region.

10. A semiconductor device comprising:

an active pattern having sidewalls defined by a device isolation pattern on a substrate, the active pattern having an upper portion protruding from a top surface of the device isolation pattern;

a liner insulating layer extending between the active pattern and the device isolation pattern;

spacers provided on sidewalls of the liner insulating layer;

a gate structure on the active pattern; and

source/drain regions at both sides of the gate structure,

wherein the liner insulating layer comprises:

a first liner insulating layer extending between the active pattern and the device isolation pattern, and

a second liner insulating layer having a first portion between the first liner insulating layer and the device isolation pattern, and a second portion between the source/drain regions and the spacers, the second portion protruding above the top surface of the device isolation pattern to define a lower portion of each of the source/drain regions.

11. The semiconductor device of claim 10 ,

wherein each of the source/drain regions comprises: a first portion defined by the second liner insulating layer; and a second portion protruding upward from the second liner insulating layer.

12. The semiconductor device of claim 11 , wherein bottom surfaces of the source/drain regions are in contact with a top surface of the first liner insulating layer.

13. The semiconductor device of claim 11 , wherein a top surface of the first liner insulating layer is disposed at a substantially same level as or a lower level than the top surface of the device isolation pattern.

14. The semiconductor device of claim 11 ,

wherein the spacers are spaced apart from the source/drain regions with the second liner insulating layer interposed therebetween, and

wherein the first liner insulating layer is formed of a material having an etch selectivity with respect to both the second liner insulating layer and the spacers.

15. The semiconductor device of claim 11 , wherein a portion of an upper portion of the active pattern is inserted in the lower portion of the each of the source/drain regions.

16. The semiconductor device of claim 10 , wherein the substrate includes an NMOSFET region and a PMOSFET region,

wherein the active pattern includes a first active pattern on the NMOSFET region and a second active pattern on the PMOSFET region, and

wherein the source/drain regions include first source/drain region on the first active pattern and second source/drain region on the second active pattern.

17. The semiconductor device of claim 16 , wherein the first source/drain region includes a material of which a lattice constant is substantially equal to or smaller than that of the substrate, and

wherein the second source/drain region includes a material of which a lattice constant is greater than that of the substrate.

18. A semiconductor device comprising:

an active pattern protruding from a substrate;

a gate structure intersecting the active pattern; and

source/drain regions at both sides of the gate structure,

wherein the active pattern comprises: a first portion overlapping with the gate structure; and second portions overlapping with the source/drain regions,

wherein top surfaces of the second portions of the active pattern are lower than a top surface of the first portion of the active pattern, and

wherein upper portions of the second portions of the active pattern are inserted into lower portions of the source/drain regions, respectively.

19. The semiconductor device of claim 18 , wherein the second portions of the active pattern have rounded top surfaces having curvatures convex in a direction away from the substrate.