Source and drain structure with reduced contact resistance and enhanced mobility
A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.
1. A semiconductor device, comprising:
a semiconductor substrate;
first and second fin active regions extruding from the semiconductor substrate and extending lengthwise along a first direction, the first and second fin active regions separated by an isolation feature in the semiconductor substrate;
first and second gate stacks extending along a second direction perpendicular to the first direction, wherein the first gate stack is disposed on the first fin active region and the second gate stack is disposed on the second fin active region;
first epitaxially grown source/drain features formed on the first fin active region on adjacent sides of the first gate stack;
second epitaxially grown source/drain features formed on the second fin active region on adjacent sides of the second gate stack;
third epitaxially grown source/drain features adjacent to the first epitaxially grown source/drain features;
fourth epitaxially grown source/drain features adjacent to the second epitaxially grown source/drain features; and
dielectric layers disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region,
wherein the first and third epitaxially grown source/drain features are separated from each other by one of the dielectric layers, and the second and fourth epitaxially grown source/drain features are merged together to form a common source/drain feature,
wherein the first epitaxially grown source/drain features extend vertically into the first fin active region at a first depth, the second epitaxially grown source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.
2. The semiconductor device of claim 1 , wherein the dielectric layers are also disposed along a top surface of the isolation feature.
3. The semiconductor device of claim 1 , wherein the first fin active region includes a p-type doped well, and the second fin active region includes a n-type doped well.
4. The semiconductor device of claim 1 , wherein the first epitaxially grown source/drain features are part of a logic device, and the second epitaxially grown source/drain features are part of a memory device.
5. The semiconductor device of claim 1 , wherein the dielectric layers include a silicon oxynitride film, a silicon nitride film on the silicon oxynitride film, and a low-k dielectric film on the silicon nitride film.
6. The semiconductor device of claim 1 , wherein the common source/drain feature and a top surface of the isolation feature defines an airgap therebetween.
7. The semiconductor device of claim 1 , wherein the dielectric layers are first dielectric layers, further comprising:
first gate spacers disposed along sidewalls of the first gate stack;
second gate spacers disposed along sidewalls of the second gate stack; and
second dielectric layers disposed along sidewalls of the first gate spacers, wherein each of the second dielectric layers is disposed between one of the first gate spacers and one of the first epitaxially grown source/drain features, wherein the first and the second dielectric layers include a same dielectric composition.
8. The semiconductor device of claim 7 , wherein the second dielectric layers are in direct contact with the first gate spacers.
9. A semiconductor device, comprising:
a semiconductor substrate;
first and second fin active regions extruding from the semiconductor substrate and extending lengthwise along a first direction, the first and second fin active regions separated by an isolation feature in the semiconductor substrate;
first and second gate stacks extending along a second direction perpendicular to the first direction, wherein the first gate stack is disposed on the first fin active region and the second gate stack is disposed on the second fin active region;
first source/drain features formed on the first fin active region on adjacent sides of the first gate stack;
second source/drain features formed on the second fin active region on adjacent sides of the second gate stack;
dielectric layers directly on all sidewalls of the first fin active region on the adjacent sides of the first gate stack and directly on a first portion of the isolation feature; and
an interlayer dielectric (ILD) layer directly on all sidewalls of the second fin active region on the adjacent sides of the second gate stack and directly on a second portion of the isolation feature different from the first portion, wherein the ILD layer is also directly on the dielectric layers.
10. The semiconductor device of claim 9 , wherein along the second direction, the first source/drain features are disposed between portions of the dielectric layers.
11. The semiconductor device of claim 9 , wherein the first source/drain features extend into the first fin active region by a first depth, the second source/drain features extend into the second fin active region by a second depth, and the first depth is greater than the second depth.
12. The semiconductor device of claim 11 , wherein the first depth is in a range between 55 nm to 65 nm.
13. The semiconductor device of claim 11 , wherein the second depth is in a range between 45 nm to 55 nm.
14. The semiconductor device of claim 9 , wherein the dielectric layers are first dielectric layers, further comprising:
first gate spacers disposed along sidewalls of the first gate stack;
second gate spacers disposed along sidewalls of the second gate stack; and
second dielectric layers disposed along sidewalls of the first gate spacers,
wherein the first and the second dielectric layers include a same dielectric composition,
wherein the first gate spacers are in direct contact with the second dielectric layers and the second gate spacers are in direct contact with the ILD layer.
15. The semiconductor device of claim 9 , wherein the first source/drain features are portions of a first transistor, the second source/drain features are portions of a second transistor, and the first transistor is part of a logic device and the second transistor is part of a memory device.
16. A semiconductor device, comprising:
a semiconductor substrate;
first and second fin active regions extruding from the semiconductor substrate and extending lengthwise along a first direction, the first and second fin active regions separated by an isolation feature in the semiconductor substrate;
first and second gate stacks extending along a second direction perpendicular to the first direction, wherein the first gate stack is disposed on the first fin active region and the second gate stack is disposed on the second fin active regions;
first and second gate spacers along sidewalls of the first and second gate stacks, respectively;
first source/drain features formed on the first fin active region on adjacent sides of the first gate stack;
second source/drain features formed on the second fin active region on adjacent sides of the second gate stack; and
dielectric layers having first segments disposed along sidewalls of the first fin active region and second segments over sidewalls of the first gate spacers, wherein the first segments are distanced and separated from the second segments by the first source/drain features along the first direction, and a top surface of the second segments are above a top surface of the first segments.
17. The semiconductor device of claim 16 , wherein the dielectric layers are also disposed along a top surface of the isolation feature.
18. The semiconductor device of claim 16 , further comprising:
third source/drain features formed over a third fin active region; and
fourth source/drain features formed over a fourth fin active region,
wherein the first fin active region is adjacent the third fin active region along the second direction, and the second fin active region is adjacent the fourth fin active region along the second direction,
wherein the dielectric layers separate the first source/drain features from the second source/drain features.
19. The semiconductor device of claim 18 , wherein the second fin active region merges with the fourth fin active region at a merged region, and an air gap is formed under the merged region.
20. The semiconductor device of claim 16 , wherein a portion of the second segment is laterally disposed between one of the first gate spacers and one of the first source/drain features.