IP Library Granted Patent US 10,103,113
Granted Patent B2
US 10,103,113 · App. 15/172,279 · Granted Oct 16, 2018

Method of manufacturing printed circuit board

Inventors: Young-Joo Ko (Gyeonggi-do, KR); Tae-Hyuk Ko (Gyeonggi-do, KR); Hyeung-Do Lee (Gyeonggi-do, KR)
Assignee: DAEDUCK ELECTRONICS CO., LTD.
H01L24/03H05K3/0026H05K3/0035H05K3/0073H05K3/0079H05K3/10H05K3/40H05K3/4038H05K3/4061H05K3/429H05K3/4644H05K3/4679H05K3/4697H01L24/48H01L2224/0347H01L2224/16145H01L2224/48091H01L2224/48227H01L2224/73257H01L2924/00014H01L2924/181H05K1/182H05K2201/10674H05K2203/025H05K2203/107Y10T29/4913Y10T29/49165Y10T29/49169
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Quick Facts
Patent No.
US 10,103,113
App. No.
15/172,279
Granted
Oct 16, 2018
Kind
B2
Abstract

A step of forming bump pads on the surface of the substrate corresponding to the cavity region, and covering the whole surface with a second insulating layer, forming a copper barrier on the surface of a second insulating layer corresponding to the cavity region for protection of the second insulating layer, forming a third insulating layer, and forming a copper layer for electrical circuit. A mask is formed on the copper later of the external circuit so that only the cavity region is exposed. The cavity is formed by laser-drilling only the surface-exposed area of the third insulating layer. The bottom copper layer protects the second insulating layer and bump pads underneath from laser damages. The copper barrier is removed by chemical etch after the laser drill. The second insulating layer with the bottom surface exposed will be removed via sand blast process, exposing the bump pads fabricated.

Claims (10)

1. A method of fabricating a printed circuit board having a cavity for embedding a chip wherein electrodes of said chip are electrically connected to bump pads which are formed on a bottom surface of the cavity, comprising the steps of:

(a) forming a first copper layer with a first circuit pattern transferred including the bump pads on a first insulating layer of the printed circuit board at a location corresponding to the cavity;

(b) forming a second insulating layer and then a second copper layer on a top surface of the first copper layer, wherein the second insulating layer is made of material having no glass fiber so that the second insulating layer is removable through a sand blast process, and wherein the second copper layer is on a top surface of the second insulating layer;

(c) forming a copper barrier on the top surface of the second insulating layer at a location corresponding to the cavity that is going to be made by selectively etching the second copper layer in accordance with a second circuit pattern, whereby the top surface of the second insulating layer is covered with the copper barrier and a portion of the second copper layer not being etched;

(d) forming a third insulating layer on top of the portion of the second copper layer not being etched and on a surface of the copper barrier;

(e) forming a third copper layer with a third circuit pattern transferred on top of the third insulating layer;

(f) selectively etching and removing a portion of the third copper layer and a portion of the third insulating layer at a location corresponding to the cavity via a laser drill, thereby forming an opening where the copper barrier is exposed at a bottom of the opening, wherein the opening is a part of the cavity;

(g) selectively coating a portion of the third copper layer that is not removed via the laser drill with an etch mask such that the copper barrier is not protected by the etch mask and an uncoated surface of the third insulating layer corresponds to a wall of the cavity;

(h) selectively eliminating the copper barrier of which a surface of the copper barrier is exposed and not protected by the etch mask with a chemical etching solution, thereby exposing a portion of a surface of the second insulating layer at the bottom of the opening;

(i) selectively etching and removing a portion of the second insulating layer of which a surface is of the second insulating layer exposed through the sand blast process, thereby forming the cavity having a bottom surface on the first insulating layer, wherein the bump pads that are formed on the first insulating layer are exposed at the bottom of the opening that is part of the cavity.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2016
From: KO, YOUNG-JOO; KO, TAE-HYUK; LEE, HYEUNG-DO
To: DAEDUCK ELECTRONICS CO., LTD.
Reel/Frame 039098/0922 →
Priority Claims (1)
KR 10-2016-021772 · Feb 24, 2016 · national
Continuity (1)
Related Publication 20170243841A1 · Aug 24, 2017
Cited By (4)
US 12,211,781 US 12,212,149 US 12,418,989 US 12,672,228