Semiconductor die fabrication methods
Systems and methods are disclosed for fabricating a semiconductor die that includes one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.
1. A method of fabricating a semiconductor die comprising:
forming a bulk silicon substrate having a high-resistivity portion;
forming a silicon-germanium bipolar transistor on the bulk silicon substrate, the silicon-germanium bipolar transistor configured as a power amplifier, the bulk silicon substrate including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the bulk silicon substrate further including a trench disposed adjacent to the low-resistivity well;
integrating a front-end module on the high-resistivity bulk silicon substrate, the front-end module including the power amplifier, a switch, and a plurality of filters; and
forming a complementary metal oxide semiconductor field-effect transistor device on the bulk silicon substrate.
2. The method of claim 1 further comprising implanting a low-resistivity substrate on a top surface of the substrate and disposing one or more digital circuit devices on the low-resistivity substrate.
3. The method of claim 2 wherein the low-resistivity substrate is implanted so as to at least partially surround a radio frequency element of the front-end module.
4. The method of claim 1 wherein the bulk silicon substrate is grown using a silicon seed.
5. The method of claim 1 wherein the silicon-germanium bipolar transistor conditions or creates electronic signals.
6. The method of claim 1 further comprising forming a low-resistivity epitaxial layer adjacent to a first portion of a top surface of the bulk silicon substrate at least partially above the high-resistivity portion.
7. The method of claim 6 further comprising destroying at least a portion of the low-resistivity layer to restore a high-resistivity characteristic in a selected region of the bulk silicon substrate.
8. The method of claim 7 wherein destroying the at least the portion of the low resistivity layer is performed by treating a surface of the semiconductor die with Argon gas.
9. The method of claim 7 further comprising disposing a passive device above the selected region of the bulk silicon substrate.
10. The method of claim 6 wherein the low-resistivity epitaxial layer includes material from an implanted sub-collector region of the silicon-germanium bipolar transistor that has out-diffused during processing of the silicon-germanium bipolar transistor.
11. The method of claim 1 wherein the low-resistivity well at least partially surrounds the silicon-germanium bipolar transistor.
12. The method of claim 1 wherein the low-resistivity well provides at least partial electrical isolation between the silicon-germanium bipolar transistor and one or more elements of the front-end module.
13. A method of fabricating a semiconductor die comprising:
forming a substrate having a high-resistivity portion;
forming a silicon-germanium bipolar transistor on the substrate, the silicon-germanium bipolar transistor configured as a power amplifier, the substrate including a low-resistivity well at least partially surrounding the silicon-germanium bipolar transistor, the substrate further including a trench disposed adjacent to the low-resistivity well;
forming a number of active devices on the substrate, the active devices including the power amplifier, a switch, and a plurality of filters; and
forming at least one additional transistor of a different material than the silicon-germanium bipolar transistor on the substrate.
14. The method of claim 13 wherein the at least one additional transistor is a complementary metal oxide semiconductor field-effect transistor.
15. The method of claim 13 wherein the substrate is a bulk silicon substrate.
16. The method of claim 13 wherein the active devices are part of a front-end module.
17. The method of claim 13 further comprising forming a low-resistivity substrate on a surface of the substrate.
18. The method of claim 17 further comprising treating at least a portion of the low-resistivity substrate with a structure altering substance.
19. The method of claim 18 further comprising disposing a passive device above the portion of the low-resistivity substrate treated with the structure altering substance.
20. The method of claim 13 wherein the low-resistivity well provides at least partial electrical isolation between the silicon-germanium bipolar transistor and the number of active devices.