IP Library › Granted Patent US 10,109,260
Granted Patent B2
US 10,109,260 · App. 14/766,986 · Granted Oct 23, 2018

Display processor and method for display processing

Inventors: Michael Staudenmaier (Munich, DE); Vincent Aubineau (Gif sur Yvette, FR); Anton Rozen (Gedera, IL)
Assignee: NXP USA, INC.
G09G5/397G06T11/60G09G5/14G09G2340/12
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Quick Facts
Patent No.
US 10,109,260
App. No.
14/766,986
Granted
Oct 23, 2018
Kind
B2
Abstract

A display processor device is for processing display image data by overlaying a multitude of image layers. Pixel values of at least one of the image layers are stored in a memory and may comprise pixels values having a single predefined value, such as transparency. The display processor has a fetch unit for selectively fetching stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask indicative of pixels values having the single predetermined value. Advantageously the bandwidth for accessing the memory is reduced, because less pixel data values need be retrieved. Power consumption may be reduced, and slower memories may be applied.

Claims (23)

1. A display processor device for processing display image data by overlaying a multitude of image layers to display images on a display with a display area of the entire display, the display processor comprising:

a memory configured to store pixel values of at least one of the image layers, wherein the display image data comprises one or more pixel values of a single predefined value;

a fetch unit, coupled to the memory, and configured to selectively fetch stored pixel values from the memory by skipping stored pixels values having the single predefined value according to a fetch mask, wherein the fetch mask spans the display area and corresponds to pixels values having the single predetermined value.

2. The display processor device as claimed in claim 1 , wherein the fetch mask is a bit mask having bit values, each bit value indicating whether a corresponding pixel has the single predefined value.

3. The display processor device as claimed in claim 1 , wherein the fetch mask is a bit mask having bit values, each bit value indicating whether a corresponding set of pixels have the single predefined value.

4. The display processor device as claimed in claim 3 , wherein the memory data amount of the pixel values of the set of pixels corresponds to a retrieval unit having multiple bytes retrievable from the memory by a single memory access operation.

5. The display processor device as claimed in claim 1 , wherein each layer of the multitude of image layers has a corresponding fetch mask.

6. The display processor device as claimed in claim 1 , wherein the fetch unit is arranged for retrieving the fetch mask from the memory.

7. The display processor device as claimed in claim 1 , wherein the fetch unit is arranged for generating the fetch mask for an image layer based on fetching said layer initially in full from the memory.

8. The display processor device as claimed in claim 1 , wherein the fetch unit is arranged for preloading the fetch mask for an image layer before fetching said layer from the memory.

9. The display processor device as claimed in claim 1 , wherein the fetch mask is available in a compressed form and the fetch unit is arranged for decompressing the fetch mask.

10. The display processor device as claimed in claim 1 , wherein the single predefined value is indicative of a transparency of the pixel in the overlaying.

11. The display processor device as claimed in claim 1 , wherein the single predefined value is indicative of a single color of the pixel.

12. The method of generating display image data as claimed in claim 1 , comprising generating the fetch mask for an image layer based on processing said layer in full.

13. The method of generating display image data as claimed in claim 12 , wherein said generating the fetch mask is performed off-line before operationally generating the display image data.

14. The method of generating display image data as claimed in claim 12 , wherein the method comprises compressing the fetch mask.

15. An integrated circuit comprising at least one electronic device according to claim 1 .

16. A method of generating display image data displayed on a display with a display area of the entire display, the method comprising:

storing pixel values of at least one image layer of a plurality of image layers of the display image data;

selectively fetching stored pixel values from the memory by skipping stored pixels values having a single predefined value according to a fetch mask indicative of pixels values having the single predetermined value, wherein the fetch mask spans the display area.

17. The method of generating display image data as claimed in claim 16 , wherein the fetch mask is a bit mask having bit values, each bit value indicating whether a corresponding pixel has the single predefined value.

18. The method of generating display image data as claimed in claim 16 , wherein each layer of the multitude of image layers has a corresponding fetch mask, or only a subset of the multitude of image layers has a corresponding fetch mask.

19. The method of generating display image data as claimed in claim 16 , comprising preloading the fetch mask for an image layer before fetching said layer from the memory.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2015
From: STAUDENMAIER, MICHAEL; AUBINEAU, VINCENT; ROZEN, ANTON
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036294/0092 →
Continuity (1)
Related Publication 20150379971A1 · Dec 31, 2015