Electronic package and manufacturing method thereof
An electronic package including a middle patterned conductive layer, a first redistribution circuitry disposed on a first surface of the middle patterned conductive layer and a second redistribution circuitry disposed on a second surface of the middle patterned conductive layer is provided. The middle patterned conductive layer has a plurality of middle conductive pads. The first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements. Each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section. The second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements. Each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section.
1. An electronic package, comprising:
a middle patterned conductive layer having a first surface, a second surface opposite to the first surface and a plurality of middle conductive pads;
a first redistribution circuitry disposed on the first surface of the middle patterned conductive layer and comprising a first patterned conductive layer, wherein the first patterned conductive layer has a plurality of first conductive elements, each of the first conductive elements has a first conductive pad and a first conductive via that form a T-shaped section, and each of the first conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad; and
a second redistribution circuitry disposed on the second surface of the middle patterned conductive layer and comprising a second patterned conductive layer, wherein the second patterned conductive layer has a plurality of second conductive elements, each of the second conductive elements has a second conductive pad and a second conductive via that form an inversed T-shaped section, and each of the second conductive via connects the corresponding middle conductive pad and is tapering facing towards the corresponding middle conductive pad.
2. The electronic package according to claim 1 , further comprising:
a chip disposed on the first redistribution circuitry.
3. The electronic package according to claim 2 , wherein the chip has an active surface and a plurality of conductive pillars on the active surface, and the conductive pillars of the chip are connected to the first redistribution circuitry.
4. The electronic package according to claim 2 , further comprising:
an encapsulant disposed on the first redistribution circuitry and encapsulating the chip.
5. The electronic package according to claim 4 , wherein the encapsulant exposes a back surface of the chip opposite to the active surface.
6. The electronic package according to claim 1 , wherein the first redistribution circuitry comprises a first dielectric layer, the middle patterned conductive layer is embedded in the first dielectric layer, and a portion of the first surface and the entire of the second surface of the middle patterned conductive layer are exposed from the first dielectric layer.
7. The electronic package according to claim 6 , wherein the first patterned conductive layer is disposed on the first dielectric layer and the first conductive vias pass through the first dielectric layer.
8. The electronic package according to claim 1 , wherein the second redistribution circuitry comprises a second dielectric layer covering the second surface of the middle patterned conductive layer and exposing the second surface of the middle patterned conductive layer.
9. The electronic package according to claim 8 , wherein the second patterned conductive layer is disposed on the second dielectric layer and the second conductive vias pass through the second dielectric layer.
10. The electronic package according to claim 1 , further comprising:
a plurality of conductive terminals disposed on the second redistribution circuitry.
11. The electronic package according to claim 10 , further comprising:
a passivation layer disposed on the second redistribution circuitry opposite to the middle patterned conductive layer, wherein the passivation layer has a plurality of openings exposing a portion of the second redistribution circuitry and the conductive terminals are disposed corresponding to the openings.