IP Library Granted Patent US 10,141,223
Granted Patent B2
US 10,141,223 · App. 15/869,107 · Granted Nov 27, 2018

Method of improving micro-loading effect when recess etching tungsten layer

Inventors: Li-Chiang Chen (Tainan, TW); Fu-Che Lee (Taichung, TW); Ming-Feng Kuo (Tainan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L21/76877H01L21/28568H01L21/31058H01L21/32115H01L21/32136H01L27/10891H01L21/76843
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Quick Facts
Patent No.
US 10,141,223
App. No.
15/869,107
Granted
Nov 27, 2018
Kind
B2
Abstract

A method of improving micro-loading effect when recess etching a tungsten layer. A substrate having trenches thereon is provided. A tungsten layer is deposited on the substrate and in the trenches. A planarization process is performed to form a planarization layer on the tungsten layer. A first etching process is performed to etch the planarization layer and the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1 until the planarization layer is completely removed. A second etching process is performed to etch the remainder of the tungsten layer to recess the tungsten layer within the trenches.

Claims (13)

1. A method for improving micro-loading effect when recess etching a tungsten layer, comprising:

providing a semiconductor substrate having a main surface, wherein a plurality of trenches is formed in the semiconductor substrate;

blanket depositing a tungsten layer on the semiconductor substrate, wherein the plurality of trenches is filled with the tungsten layer;

subjecting the tungsten layer to a planarization process to form a planarization layer on the tungsten layer;

performing a first etching process to completely remove the planarization layer and partially remove the tungsten layer with an etch selectivity of planarization layer:tungsten layer=1:1; and

performing a second etching process to etch remainder of the tungsten layer until a top surface of the tungsten layer is lower than the main surface of the semiconductor substrate.

2. The method according to claim 1 , wherein the planarization process comprises:

etching the tungsten layer with a plasma formed of a gas selected from the group consisting of C 4 F 6 , C 4 F 8 , or SiCl 4 /CF 4 while providing a pulse bias condition, and currently depositing the planarization layer on the tungsten layer.

3. The method according to claim 1 , wherein the pulse bias condition comprises the following parameters: a pulse frequency of 13.56 MHz, a bias power of 100 W, and a duty cycle (DC) of 20%.

4. The method according to claim 1 , wherein the planarization layer is a polymer layer.

5. The method according to claim 1 , wherein top surfaces of the tungsten layer within the plurality of trenches are in the same horizontal level.

6. The method according to claim 1 , wherein the first etching step is not provided with any pulse bias, and wherein the planarization layer and the tungsten layer are etched with a plasma formed of a gas containing SF 6 and Ar.

7. The method according to claim 1 , wherein the second etching step is performed by etching the tungsten layer with a plasma formed by SF 6 and Ar while providing a pulse bias.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2018
From: CHEN, LI-CHIANG; LEE, FU-CHE; KUO, MING-FENG
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 045282/0368 →
Priority Claims (1)
CN 2017 1 0216987 · Apr 5, 2017 · national
Continuity (1)
Related Publication 20180294188A1 · Oct 11, 2018