Flip-chip amplifier with termination circuit
Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.
1. A power amplifier module comprising:
a flip-chip power amplifier die including a power amplifier configured to amplify a radio frequency signal;
a first circuit element included in a matching network that is configured to provide impedance matching at a fundamental frequency of the radio frequency signal; and
a second circuit element included in a harmonic termination circuit, the second circuit element and the first circuit element being electrically connected to an output of the power amplifier by way of different bumps.
2. The power amplifier module of claim 1 further comprising an input termination circuit electrically connected to an input of the power amplifier.
3. The power amplifier module of claim 1 wherein the power amplifier is a multi-stage power amplifier.
4. The power amplifier module of claim 1 wherein the power amplifier includes a gallium arsenide bipolar transistor.
5. The power amplifier module of claim 1 wherein the flip-chip power amplifier die is mounted on a packaging substrate.
6. The power amplifier module of claim 5 wherein the second circuit element includes a capacitor on the packing substrate.
7. The power amplifier module of claim 6 further comprising a conductor trace coupled in series between the capacitor and a bump of the different bumps.
8. The power amplifier module of claim 5 wherein the different bumps are coupled to different respective bump pads on the packaging substrate.
9. The power amplifier module of claim 1 further comprising a first conductor trace coupled between the first circuit element and a first bump of the different bumps, and a second conductor trace coupled between the second circuit element and a second bump of the different bumps.
10. A flip-chip system comprising:
a flip-chip die including a radio frequency signal path configured to provide a radio frequency signal at a node;
a first circuit element electrically connected to the node by way of a first bump, the first circuit element being included in a matching network configured to provide impedance matching at a fundamental frequency of the radio frequency signal; and
a second circuit element electrically connected to the node by way of a second bump, the second circuit element being included in a harmonic termination circuit.
11. The flip-chip system of claim 10 wherein the harmonic termination circuit is configured to terminate at a phase corresponding to a second harmonic of the radio frequency signal.
12. The flip-chip system of claim 10 further comprising another harmonic termination circuit coupled to the node.
13. The flip-chip system of claim 10 wherein the radio frequency signal path includes a power amplifier having an output electrically connected to the node.
14. The flip-chip system of claim 10 wherein the flip-chip die is mounted on a laminate substrate.
15. The flip-chip system of claim 14 wherein the second circuit element includes a capacitor on the laminate substrate.
16. The flip-chip system of claim 15 further comprising a conductor trace coupled in series between the second bump and the capacitor.
17. The flip chip system of claim 10 wherein the flip-chip die is mounted on a packaging substrate, the first circuit element is coupled to the node by way of a first pad on the packaging substrate and the first bump, and the second circuit element is coupled to the node by way of a second pad on the packaging substrate and the second bump.
18. A method of fabricating termination circuits associated with a flip-chip die, the method comprising:
forming connections for receiving a flip-chip die on a substrate;
forming a first termination circuit on and/or in the substrate, the first termination circuit configured to providing impedance matching at a fundamental frequency of a radio frequency signal of the flip-chip die; and
forming a second termination circuit on and/or in the substrate, the second termination circuit configured to terminate at a phase corresponding to a harmonic frequency of the radio frequency signal of the flip-chip die, the second termination circuit being separate from the first termination circuit.
19. The method of claim 18 wherein the first termination includes a first conductor trace on the substrate, and the second termination circuit includes a second conductor trace on the substrate.
20. The method of claim 18 wherein the first termination includes a first capacitor on the substrate, and the second termination circuit includes a second capacitor on the substrate.
21. The method of claim 18 wherein forming the second termination circuit includes forming a conductor trace on the substrate and mounting a capacitor on the substrate.