Through-vias and methods of forming the same
An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.
1. A method comprising:
from a front side of a substrate, forming a first through-via extending from a front surface of the substrate into the substrate;
performing a backside grinding on the substrate from a backside of the substrate, wherein the first through-via is revealed from a back surface of the substrate;
forming a first through-opening from the backside of the substrate;
filling the first through-opening with a dielectric material;
forming a second through-opening in the dielectric material; and
filling the second through-opening with a conductive material to form a second through-via.
2. The method of claim 1 further comprising:
before the filling the first through-opening with the dielectric material, forming a conductive region on sidewalls of the first through-opening.
3. The method of claim 1 , wherein the filling the first through-opening with the dielectric material comprising filling a polymer in the first through-opening.
4. The method of claim 1 further comprising forming an active device at the front surface of the substrate.
5. The method of claim 1 , wherein the forming the first through-opening is performed after the backside grinding.
6. The method of claim 4 , wherein a portion of the active device extends into the substrate.
7. The method of claim 1 further comprising, after the forming the first through-opening in the substrate and before the filling the first through-opening with the dielectric material:
forming an isolation ring in the first through-opening, wherein the isolation ring is on a sidewall of the substrate; and
forming a conductive ring in the first through-opening, wherein the conductive ring is encircled by the isolation ring.
8. The method of claim 1 , wherein in the forming the first through-opening from the backside of the substrate, the first through-opening stops on a dielectric layer on the front side of the substrate, and in the forming the second through-opening, a conductive feature on the front side of the substrate is exposed.
9. A method comprising:
forming an active device at a front surface of a substrate;
performing a backside grinding on the substrate to expose a first through-via in the substrate;
etching the substrate from backside to form a first through-opening penetrating through the substrate, wherein the first through-opening stops on a dielectric layer on a front side of the substrate;
forming a conductive material on a sidewall of the first through-opening, wherein the conductive material comprises a ring encircling the first through-opening;
filling the first through-opening with a dielectric material;
etching the dielectric material to form a second through-opening, wherein the second through-opening is encircled by the ring, and the second through-opening penetrates through the dielectric layer, with a conductive feature on the front side of the substrate exposed to the second through-opening; and
filling the second through-opening with an additional conductive material to form a second through-via.
10. The method of claim 9 , wherein the conductive material further forms a redistribution line electrically coupled to the first through-via, wherein the redistribution line and the ring are formed in common steps.
11. The method of claim 9 further comprising, before the forming the conductive material, forming an isolation ring on sidewalls of the first through-opening.
12. The method of claim 9 further comprising electrically grounding the ring.
13. The method of claim 9 , wherein the filling the first through-opening with the dielectric material comprises filling with a polymer.
14. The method of claim 9 further comprising forming a solder region on the backside of the substrate, wherein the solder region is electrically coupled to the second through-via.
15. A method comprising:
forming an active device at a front surface of a semiconductor substrate;
forming a dielectric layer on a back surface of a semiconductor substrate, wherein the front surface and the back surface are opposite surfaces of the semiconductor substrate;
etching the dielectric layer and the semiconductor substrate from a backside of the semiconductor substrate to form a first through-opening penetrating through the dielectric layer and the semiconductor substrate;
forming a dielectric isolation layer on a sidewall of the first through-opening;
depositing a conductive material, wherein the conductive material comprises a first portion on the dielectric layer, and a second portion extending into the first through-opening to form a ring encircling the first through-opening;
patterning the conductive material, wherein a remaining portion of the first portion of the conductive material forms a redistribution line, and wherein the ring remains after the patterning;
filling the first through-opening with a dielectric material;
etching the dielectric material to form a second through-opening penetrating through the dielectric material, wherein the second through-opening is encircled by the ring; and
filling the second through-opening with an additional conductive material to form a first through-via.
16. The method of claim 15 further comprising, before the forming the dielectric layer, performing a backside grinding on the back surface of the semiconductor substrate to expose a second through-via in the semiconductor substrate.
17. The method of claim 16 , wherein the redistribution line is electrically coupled to the second through-via.
18. The method of claim 15 , wherein the filling the first through-opening with the dielectric material comprises filling with a polymer.
19. The method of claim 15 further comprising, after the second through-opening penetrates through the semiconductor substrate, further etching an additional dielectric layer on a front side of the semiconductor substrate to expose a conductive feature.
20. The method of claim 15 , wherein in the etching the semiconductor substrate, the first through-opening stops on an additional dielectric layer on the front surface of the semiconductor substrate, and in the forming the second through-opening, a conductive feature at the front surface of the semiconductor substrate is exposed.