Deep trench capacitor with a filled trench and a doped region serving as a capacitor electrode
View Patent ↗The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes are insulated with one another. The semiconductor structure further includes a plug in the capacitor and surrounded by the plurality of electrodes.
1. A semiconductor structure, comprising:
a semiconductive substrate;
a doped region in the semiconductive substrate, the doped region having a conductivity type opposite to the conductivity type of the semiconductive substrate;
a capacitor in the doped region, the capacitor comprising a plurality of electrodes and the plurality of electrodes being insulated from one another;
a first dielectric disposed on one of the plurality of electrodes; and
a multi-layer structure extending within the capacitor and surrounded by the first dielectric, wherein the multi-layer structure comprises a second dielectric contacting the first dielectric and exposing a portion of the first dielectric.
2. The semiconductor structure of claim 1 , wherein the multi-layer structure further includes a conductive material surrounded by the second dielectric.
3. The semiconductor structure of claim 1 , wherein the multi-layer structure is electrically insulated from the plurality of electrodes.
4. The semiconductor structure of claim 1 , wherein the multi-layer structure is electrically coupled to one of the plurality of electrodes.
5. The semiconductor structure of claim 1 , wherein the multi-layer structure further includes a same material as one of the plurality of electrodes.
6. The semiconductor structure of claim 1 , wherein each of the plurality of electrodes is extending over a portion of a top surface of the semiconductive substrate.
7. The semiconductor structure of claim 1 , wherein the doped region is electrically insulated from one of the plurality of electrodes.
8. The semiconductor structure of claim 1 , further comprising an interconnect structure comprising a plurality of conductive vias electrically coupled to the doped region and each of the plurality of electrodes, respectively.
9. The semiconductor structure of claim 1 , wherein the multi-layer structure further comprises tungsten.
10. The semiconductor structure of claim 1 , wherein the multi-layer structure has an aspect ratio from about 20 to about 80.