Hybrid substrate engineering in CMOS finFET integration for mobility improvement
A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.
1. A hybrid complementary metal oxide semiconductor (CMOS) device, comprising:
a semiconductor-on-insulator (SOI) substrate including a semiconductor layer, a buried dielectric and a base substrate, wherein the semiconductor layer includes a (100) wafer and the base substrate includes a (110) wafer and device channels for the semiconductor layer and the base substrate are in a <110> direction;
an N-well region including:
a first epitaxially grown extended region formed from the base substrate, with the entire first epitaxially grown extended region formed to a height of a top surface of the buried dielectric layer; and
a second epitaxially grown region grown from the extended region, wherein the second epitaxially grown region includes p-type field-effect transistor (PFET) fins formed on the base substrate with rectangular-shaped source and drain regions, that mimic a shape of the PFET fins, on the PFET fins; and
N-type field-effect transistor (NFET) fins formed in the semiconductor layer outside the N-well region with rectangular-shaped source and drain regions, that mimic a shape of the NFET fins, on the NFET fins.
2. The device as recited in claim 1 , wherein the PFET fins are formed on pedestals formed in the base substrate.
3. The device as recited in claim 1 , wherein PFET fins are extended to a height of the semiconductor layer.
4. The device as recited in claim 1 , wherein NFET fins are provided to a height of the semiconductor layer.
5. The device as recited in claim 1 , wherein the first epitaxially grown extended region includes Si.
6. The device as recited in claim 1 , wherein the second epitaxially grown region includes SiGe.
7. The device as recited in claim 6 , wherein the SiGe includes 50-100 atomic percent Ge.
8. A hybrid complementary metal oxide semiconductor (CMOS) device, comprising:
a silicon-on-insulator (SOI) substrate including a silicon layer, a buried dielectric and a silicon base substrate, wherein the silicon layer includes a (100) wafer and the base substrate includes a (110) wafer and device channels for the silicon layer and the base substrate are in a <110> direction;
an N-well region including:
an epitaxially grown extended region formed from the base substrate, with the entire epitaxially grown extended region formed to a height of a top surface of the buried dielectric layer; and
an epitaxially grown SiGe region grown from the extended region, wherein the SiGe region includes p-type field-effect transistor (PFET) fins formed on the base substrate with rectangular-shaped source and drain regions, that mimic a shape of the PFET fins, on the PFET fins; and
N-type field-effect transistor (NFET) fins formed in the silicon layer outside the N-well region with rectangular-shaped source and drain regions, that mimic a shape of the NFET fins, on the NFET fins.
9. The device as recited in claim 8 , wherein the PFET fins are formed on pedestals formed in the base substrate.
10. The device as recited in claim 8 , wherein PFET fins are extended to a height of the silicon layer.
11. The device as recited in claim 8 , wherein NFET fins are provided to a height of the silicon layer.
12. The device as recited in claim 8 , wherein the extended region includes Si.
13. The device as recited in claim 8 , wherein the SiGe region includes 50-100 atomic percent Ge.