Semiconductor device, inverter circuit, drive device, vehicle, and elevator
A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.
1. A semiconductor device comprising:
a silicon carbide layer having a first plane and a second plane;
a source electrode contacting the first plane;
a drain electrode contacting the second plane;
a first gate electrode located between the source electrode and the drain electrode;
a second gate electrode located between the source electrode and the drain electrode;
an n-type drift region located in the silicon carbide layer, the n-type drift region including a first n-type portion and a second n-type portion;
a p-type body region located in the silicon carbide layer and located between the n-type drift region and the first plane;
an n-type first source region located in the silicon carbide layer, the n-type first source region located between the p-type body region and the first plane, and the n-type first source region contacting the source electrode;
an n-type second source region located in the silicon carbide layer, the n-type second source region located between the p-type body region and the first plane, the re-type second source region contacting the source electrode, and the first gate electrode being located between the n-type first source region and the n-type second source region;
a p-type first silicon carbide region located in the silicon carbide layer, the p-type first silicon carbide region located between the n-type drift region and the first plane, the p-type first silicon carbide region contacting the source electrode, a distance between the second plane and the p-type first silicon carbide region being smaller than a distance between the second plane and the first gate electrode, the first gate electrode being located between the n-type first source region and the p-type first silicon carbide region, the p-type first silicon carbide region located between the first gate electrode and the p-type body region, and the p-type first silicon carbide region having a p-type impurity concentration higher than a p-type impurity concentration of the p-type body region;
a p-type second silicon carbide region located in the silicon carbide layer, the p-type second silicon carbide region located between the n-type drift region and the first plane, the p-type second silicon carbide region contacting the source electrode, a distance between the second plane and the p-type second silicon carbide region being smaller than a distance between the second plane and the second gate electrode, the second gate electrode being located between the n-type second source region and the p-type second silicon carbide region, the p-type second silicon carbide region located between the second gate electrode and the p-type body region, and the p-type second silicon carbide region having a p-type impurity concentration higher than the p-type impurity concentration of the p-type body region;
a first gate insulating layer located between the first gate electrode and the n-type drift region, between the first gate electrode and the p-type body region, between the first gate electrode and the p-type first silicon carbide region, and between the first gate electrode and the n-type first source region;
a second gate insulating layer located between the second gate electrode and the n-type drift region, between the second gate electrode and the p-type body region, between the second gate electrode and the p-type second silicon carbide region, and between the second gate electrode and the n-type second source region;
a p-type third silicon carbide region located in the silicon carbide layer, the p-type third silicon carbide region located between the second plane and the first gate electrode, the p-type third silicon carbide region contacting the p-type first silicon carbide region, the first n-type portion being located between the first gate insulating layer and the p-type third silicon carbide region; and
a p-type fourth silicon carbide region located in the silicon carbide layer, the p-type fourth silicon carbide region located between the second plane and the second gate electrode, the p-type fourth silicon carbide region contacting the p-type second silicon carbide region, the second n-type portion being located between the second gate insulating layer and the p-type fourth silicon carbide region, and the p-type fourth silicon carbide region separated from the p-type third silicon carbide region.
2. The semiconductor device according to claim 1 , wherein a distance between the p-type third silicon carbide region and the first gate insulating layer and a distance between the p-type fourth silicon carbide region and the second gate insulating layer are 0.05 μm to 0.2 μm.
3. The semiconductor device according to claim 1 , wherein
the n-type drift region has a first n-type region and a second n-type region located between the first n-type region and the p-type body region, the second n-type region having an impurity concentration higher than an impurity concentration of the first n-type region,
wherein the first n-type portion and the second n-type portion are located in the second n-type region.
4. The semiconductor device according to claim 3 , wherein an n-type impurity concentration of the second n-type region is 2×10 17 cm −3 to 1×10 19 cm −3 .
5. The semiconductor device according to claim 3 , wherein the n-type drift region further includes a third n-type region, the third n-type region located between the second n-type region and the p-type body region, the third n-type region having an n-type impurity concentration lower than an n-type impurity concentration of the second n-type region.
6. The semiconductor device according to claim 1 , wherein the p-type body region has a first p-type region and a second p-type region located between the first p-type region and the n-type drift region, and the second p-type region having a p-type impurity concentration higher than a p-type impurity concentration of the first p-type region.
7. The semiconductor device according to claim 1 , wherein a distance between the p-type third silicon carbide region and the p-type fourth silicon carbide region is smaller than a distance between the p-type first silicon carbide region and the p-type second gate insulating layer.
8. The semiconductor device according to claim 1 , wherein a distance between the second plane and the p-type first silicon carbide region is smaller than a distance between the second plane and the p-type third silicon carbide region, and a distance between the second plane and the p-type second silicon carbide region is smaller than a distance between the second plane and the p-type fourth silicon carbide region.
9. The semiconductor device according to claim 1 , wherein the first gate electrode and the second gate electrode extend in a first direction parallel to the first plane, and the p-type third silicon carbide region and the p-type fourth silicon carbide region extend in the first direction.
10. The semiconductor device according to claim 1 , further comprising:
a p-type fifth silicon carbide region located in the n-type drift region, the p-type fifth silicon carbide region located between the first gate electrode and the second plane, and the p-type fifth silicon carbide region extending in a first direction parallel to the first plane;
a p-type sixth silicon carbide region located in the n-type drift region, the p-type sixth silicon carbide region located between the second source region and the second plane, the p-type sixth silicon carbide region located between the p-type third silicon carbide region and the second plane, and the p-type sixth silicon carbide region extending in the first direction; and
a p-type seventh silicon carbide region located in the n-type drift region, the p-type seventh silicon carbide region located between the second gate electrode and the second plane, and the p-type seventh silicon carbide region extending in the first direction.
11. The semiconductor device according to claim 10 , further comprising:
a p-type eighth silicon carbide region located in the n-type drift region, the p-type eighth silicon carbide region extending in a second direction parallel to the first plane and vertical to the first direction, and the p-type eighth silicon carbide region contacting the p-type fifth silicon carbide region, the p-type sixth silicon carbide region, and the p-type seventh silicon carbide region; and
a p-type ninth silicon carbide region located in the n-type drift region, the p-type ninth silicon carbide region extending in the second direction, the p-type ninth silicon carbide region contacting the p-type fifth silicon carbide region, the p-type sixth silicon carbide region, and the p-type seventh silicon carbide region, and the p-type ninth silicon carbide region separated from the p-type eighth silicon carbide region.
12. The semiconductor device according to claim 1 , further comprising:
a p-type tenth silicon carbide region located between the p-type first silicon carbide region and the p-type body region, the p-type tenth silicon carbide region located between the p-type first silicon carbide region and the n-type second source region, the p-type tenth silicon carbide region contacting the source electrode, a distance between the second plane and the p-type tenth silicon carbide region being smaller than a distance between the second plane and the first gate electrode, and the p-type tenth silicon carbide region having a p-type impurity concentration higher than a p-type impurity concentration of the p-type body region,
wherein the the n-type drift region includes a fifth n-type portion, the fifth n-type portion located between the p-type first silicon carbide region and the p-type tenth silicon carbide region, the fifth n-type portion contacts the source electrode.
13. A semiconductor device comprising:
a silicon carbide layer having a first plane and a second plane;
a source electrode contacting the first plane;
a drain electrode contacting the second plane;
a first gate electrode located between the source electrode and the drain electrode, and the first gate electrode extending in a first direction parallel to the first plane;
a second gate electrode located between the source electrode and the drain electrode, and the second gate electrode extending in the first direction;
an n-type drift region located in the silicon carbide layer, the n-type drift region including a first n-type portion, a second n-type portion, a third n-type portion, and a fourth n-type portion;
a p-type body region located in the silicon carbide layer and located between the n-type drift region and the first plane;
an n-type first source region located in the silicon carbide layer, the n-type first source region located between the p-type body region and the first plane, and the n-type first source region contacting the source electrode;
an n-type second source region located in the silicon carbide layer, the n-type second source region located between the p-type body region and the first plane, the n-type second source region contacting the source electrode, and the first gate electrode being located between the n-type first source region and the n-type second source region;
a p-type first silicon carbide region located in the silicon carbide layer, the p-type first silicon carbide region located between the n-type drift region and the first plane, the p-type first silicon carbide region contacting the source electrode, a distance between the second plane and the p-type first silicon carbide region being smaller than a distance between the second plane and the first gate electrode, the first gate electrode being located between the n-type first source region and the p-type first silicon carbide region, the p-type first silicon carbide region located between the first gate electrode and the p-type body region, and the p-type first silicon carbide region having a p-type impurity concentration higher than a p-type impurity concentration of the p-type body region;
a p-type second silicon carbide region located in the silicon carbide layer, the p-type second silicon carbide region located between the n-type drift region and the first plane, the p-type second silicon carbide region contacting the source electrode, a distance between the second plane and the p-type second silicon carbide region being smaller than a distance between the second plane and the second gate electrode, the second gate electrode being located between the n-type second source region and the p-type second silicon carbide region, the p-type second silicon carbide region located between the second gate electrode and the p-type body region, and the p-type second silicon carbide region having a p-type impurity concentration higher than the p-type impurity concentration of the p-type body region;
a first gate insulating layer located between the first gate electrode and the n-type drift region, between the first gate electrode and the p-type body region, between the first gate electrode and the p-type first silicon carbide region, and between the first gate electrode and the n-type first source region;
a second gate insulating layer located between the second gate electrode and the n-type drift region, between the second gate electrode and the p-type body region, between the second gate electrode and the p-type second silicon carbide region, and between the second gate electrode and the n-type second source region;
a p-type third silicon carbide region located in the silicon carbide layer, the p-type third silicon carbide region extending in a second direction parallel to the first plane and vertical to the first direction, the p-type third silicon carbide region located between the second plane and the first gate electrode, the p-type third silicon carbide region located between the second plane and the second gate electrode, the p-type third silicon carbide region contacting the p-type first silicon carbide region and the p-type second silicon carbide region, the first n-type portion being located between the first gate insulating layer and the p-type third silicon carbide region, and the second n-type portion being located between the second gate insulating layer and the p-type third silicon carbide region; and
a p-type fourth silicon carbide region located in the silicon carbide layer, the p-type fourth silicon carbide region extending in the second direction, the p-type fourth silicon carbide region located between the second plane and the first gate electrode, the p-type fourth silicon carbide region located between the second plane and the second gate electrode, the p-type fourth silicon carbide region contacting the first silicon carbide region and the second silicon carbide region, the third n-type portion being located between the first gate insulating layer and the p-type fourth silicon carbide region, the fourth n-type portion being located between the second gate insulating layer and the p-type fourth silicon carbide region, and the p-type fourth silicon carbide region separated from the p-type third silicon carbide region.
14. The semiconductor device according to claim 13 , wherein a distance between the p-type third silicon carbide region and the first gate insulating layer and a distance between the p-type third silicon carbide region and the second gate insulating layer are 0.05 μm to 0.2 μm.
15. The semiconductor device according to claim 13 , wherein the n-type drift region has a first n-type region and a second n-type region located between the first n-type region and the p-type body region, the second n-type region having an n-type impurity concentration higher than an n-type impurity concentration of the first n-type region, and the first n-type portion and the second n-type portion are located in the second n-type region.
16. The semiconductor device according to claim 15 , wherein the n-type impurity concentration of the second n-type region is 2×10 17 cm −3 to 1×10 19 cm −3 .
17. An inverter circuit comprising the semiconductor device according to claim 1 .
18. A drive device comprising the semiconductor device according to claim 1 .
19. A vehicle comprising the semiconductor device according to claim 1 .
20. An elevator comprising the semiconductor device according to claim 1 .