IP Library Granted Patent US 10,181,450
Granted Patent B2
US 10,181,450 · App. 15/421,461 · Granted Jan 15, 2019

Method of manufacturing semiconductor device

Inventors: Seiya Isozaki (Tokyo, JP); Takashi Moriyama (Tokyo, JP); Takehiko Maeda (Gunma, JP)
Assignee: Renesas Electronics Corporation
H01L24/43H01L21/4853H01L23/4952H01L23/49582H01L24/03H01L24/05H01L24/27H01L24/33H01L24/48H01L24/73H01L24/45H01L24/49H01L2224/04042H01L2224/05554H01L2224/05624H01L2224/32225H01L2224/3303H01L2224/45144H01L2224/45147H01L2224/48227H01L2224/48247H01L2224/48465H01L2224/49171H01L2224/73215H01L2224/73265H01L2224/78301H01L2224/8385H01L2224/85181H01L2224/92247H01L2924/01029H01L2924/01046H01L2924/04941H01L2924/15311H01L2924/181
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Quick Facts
Patent No.
US 10,181,450
App. No.
15/421,461
Granted
Jan 15, 2019
Kind
B2
Abstract

A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.

Claims (29)

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) mounting a semiconductor chip having a pad and a wiring over a base material; and

(b) after the step (a), electrically connecting the pad of the semiconductor chip with a terminal of the base material via a wire comprised of copper,

wherein the semiconductor chip has:

an insulating layer,

the pad formed on a surface of the insulating layer,

the wiring formed on the surface of the insulating layer, and

an insulating film formed on the surface of the insulating layer such that the insulating film exposes a part of the pad, and such that the insulating film covers the wiring,

wherein the pad of the semiconductor chip is manufactured by the following steps (a-1) to (a-5) of:

(a-1) forming a laminated film over the surface of the insulating layer, the laminated film having a first conductive layer comprised of aluminum, a second conductive layer comprised of a material different from the first conductive layer and stacked over the first conductive layer, and a third conductive layer comprised of the same material as the first conductive layer and stacked over the second conductive layer,

(a-2) after the step (a-1), forming the pad having the first to the third conductive layers and the wiring having the first to the third conductive layers by patterning the laminated film,

(a-3) after the step (a-2), forming the insulating film over the surface of the insulating layer such that the insulating film covers the pad and the wiring,

(a-4) after the step (a-3), exposing the part of the pad from the insulating film by patterning the insulating film, and

(a-5) after the step (a-4), exposing the first conductive layer of the pad by etching the part of the pad exposed from the insulating film, and

wherein, in the step (b), a first portion of the wire is connected to a surface of the first conductive layer of the pad exposed from the insulating film.

2. The method of manufacturing a semiconductor device according to claim 1 ,

wherein in the step (b), the first portion of the wire is connected to the surface of the first conductive layer of the pad exposed from the insulating film, while applying supersonic waves to the wire.

3. The method of manufacturing a semiconductor device according to claim 1 , further comprising the step of:

after the step (a-5), forming a conductive adhesive layer over the surface of the first conductive layer exposed in the part of the pad.

4. The method of manufacturing a semiconductor device according to claim 3 ,

wherein the conductive adhesive layer contains palladium.

5. The method of manufacturing a semiconductor device according to claim 1 ,

wherein, by the step (a-5), a peripheral portion of the pad is formed to have a thickness larger than that of a central portion of the pad.

6. The method of manufacturing a semiconductor device according to claim 1 ,

wherein the semiconductor device further includes a fourth conductive layer comprised of the same material as the second conductive layer and stacked over the third conductive layer.

7. The method of manufacturing a semiconductor device according to claim 6 ,

wherein the second conductive layer and the fourth conductive layer include titanium nitride.

8. The method of manufacturing a semiconductor device according to claim 1 ,

wherein the first conductive layer is formed to have a thickness larger than that of the third conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: ISOZAKI, SEIYA; MORIYAMA, TAKASHI; MAEDA, TAKEHIKO
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 041141/0856 →
Priority Claims (1)
JP 2016-073354 · Mar 31, 2016 · national
Continuity (1)
Related Publication 20170287868A1 · Oct 5, 2017