IP Library › Granted Patent US 10,181,456
Granted Patent B2
US 10,181,456 · App. 15/461,052 · Granted Jan 15, 2019

Multi-package integrated circuit assembly with package on package interconnects

Inventor: Hyoung Il Kim (Folsom, CA)
Assignee: Intel Corporation
H01L25/0657H01L21/56H01L23/08H01L24/16H01L24/17H01L24/81H01L25/50H01L2224/16057H01L2224/16104H01L2225/06513H01L2225/06544
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Quick Facts
Patent No.
US 10,181,456
App. No.
15/461,052
Granted
Jan 15, 2019
Kind
B2
Abstract

A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A conductive interconnect can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.

Claims (28)

1. A multi-package integrated circuit assembly comprising:

a first electronic package including a first package substrate having a first die side and a first interface side;

first plurality of dies electrically coupled to the first die side of the first package substrate, the first plurality of dies staggered to expose a portion of a contact pad on a face of each die facing away from the first die side;

respective first plurality of wire bonds electrically coupling respective contact pads and the first die side;

a second electronic package including a second package substrate having a second die side and a second interface side;

a second die electrically coupled to the second die side of the second package substrate;

a conductive interconnect electrically coupling the first package substrate and the second package substrate, wherein the conductive interconnect is located from the interface side of the first package substrate to the interface side of the second package substrate;

a collective substrate attached to the first electronic package, wherein the collective substrate is located on a face of the first electronic package opposing the first package substrate, and the collective substrate is electrically coupled to the first die and the second die through the first package substrate; and

a second plurality of wire bonds electrically coupling the first interface side and the collective substrate.

2. The integrated circuit assembly of claim 1 , wherein the second die is a stacked die package having a plurality of second dies attached together and staggered to expose a portion of a contact pad on a face of each die facing away from the second die side.

3. The integrated circuit assembly of claim 2 , wherein the plurality of second dies of the second electronic package are electrically coupled to the collective substrate through the first package substrate.

4. The integrated circuit assembly of claim 1 , wherein the conductive interconnect is located within a periphery of the first plurality of dies.

5. The integrated circuit assembly of claim 1 , further comprising a plurality of conductive interconnects located from the interface side of the first package substrate to the interface side of the second package substrate, wherein the plurality of conductive interconnects are located within a periphery of the first plurality of dies.

6. The integrated circuit assembly of claim 1 , wherein the conductive interconnect is located between the first plurality of dies and the second die.

7. The integrated circuit assembly of claim 1 , wherein the conductive interconnect includes a dimension along a longitudinal axis of the conductive interconnect that is 10 μm, 500 μm, or any dimension therebetween.

8. The integrated circuit assembly of claim 1 , wherein the conductive interconnect is a solder ball, the solder ball including a flat surface.

9. The integrated circuit assembly of claim 1 , further comprising an insulative covering over the first package and a first side of the collective substrate, wherein the conductive interconnect is a solder ball, and a face of the insulative covering is coplanar with a flat surface of the solder ball.

10. A three-dimensional multi-package integrated circuit assembly comprising:

a first electronic package including a first package substrate having a first die side and a first interface side, a plurality of first package dies electrically coupled to the first die side of the first package substrate, the plurality of first package dies staggered to expose a portion of a contact pad on a face of each die facing away from the first die side;

respective first plurality of wire bonds electrically coupling respective contact pads and the first die side;

a second electronic package including a second package substrate having a second die side and a second interface side, a plurality of second package dies electrically coupled to the second die side of the second package substrate, the plurality of second package dies staggered to expose a portion of a contact pad on a face of each die facing away from the second die side;

a conductive interconnect electrically coupling the first package substrate and the second package substrate, wherein the conductive interconnect is located from the interface side of the first package substrate to the interface side of the second package substrate;

a collective substrate attached to the first electronic package, wherein the collective substrate is located on a face of the first electronic package opposing the first package substrate, and the collective substrate is electrically coupled to the first package substrate and the second package substrate, and the second package substrate is electrically coupled to the collective substrate through the first package substrate; and

a second plurality of wire bonds electrically coupling the first interface side and the collective substrate.

11. The integrated circuit assembly of claim 10 , wherein the plurality of second package dies are electrically coupled to the collective substrate through the first package substrate.

12. The integrated circuit assembly of claim 10 , wherein the conductive interconnect is located between the plurality of first package dies and the plurality of second package dies.

13. The integrated circuit assembly of claim 10 , wherein the conductive interconnect includes a dimension along a longitudinal axis of the conductive interconnect that is 10 μm, 500 μm, or any dimension therebetween.

14. The integrated circuit assembly of claim 10 , further comprising an insulative covering over the first package and a first side of the collective substrate, wherein the conductive interconnect is a solder ball, and a face of the insulative covering is coplanar with a flat surface of the solder ball.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2017
From: KIM, HYOUNG IL
To: INTEL CORPORATION
Reel/Frame 043174/0248 →
Continuity (1)
Related Publication 20180269183A1 · Sep 20, 2018