Power amplification system with envelope-based bias
Disclosed herein are power amplification systems that are dynamically biased based on a signal indicative of an envelope of the signal being amplified. The power amplification systems include a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal. The power amplification systems also include a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal. The biasing signal can improve or enhance the linearity of the power amplification systems.
1. A power amplification system comprising:
a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal, the power amplifier including a plurality of cascode amplifiers coupled in parallel; and
a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal.
2. The power amplification system of claim 1 further comprising a supply component configured to generate an envelope-based supply voltage for powering the power amplifier.
3. The power amplification system of claim 2 wherein the biasing signal is configured to enhance a linearity of the power amplifier.
4. The power amplification system of claim 1 wherein the power amplifier includes a cascode power amplifier including a first transistor and a second transistor.
5. The power amplification system of claim 4 wherein the first transistor has a gate to receive the biasing signal, a drain coupled to a supply voltage, and a source coupled to a drain of the second transistor.
6. The power amplification system of claim 5 wherein the second transistor has a gate coupled to a supplemental biasing signal and a source coupled to a ground voltage.
7. The power amplification system of claim 6 wherein the supplemental biasing signal is based on the envelope signal.
8. The power amplification system of claim 6 wherein the supplemental biasing signal is independent of the envelope signal.
9. The power amplification system of claim 4 wherein the input RF signal is received at an input RF port coupled to the gate of the second transistor and the output RF signal is provided at an output RF port coupled to the drain of the first transistor.
10. The power amplification system of claim 7 wherein the input RF port is coupled to the gate of the second transistor via an input matching component and the output RF port is coupled to the drain of the first transistor via an output matching component.
11. The power amplification system of claim 1 further comprising a bias time alignment circuit configured to align in time the biasing signal with the envelope signal.
12. The power amplification system of claim 11 further comprising an envelope alignment circuit configured to align in time the biasing signal and the envelope signal.
13. The power amplification system of claim 12 further comprising a bias shaping circuit configured to manipulate a shape of the biasing signal to enhance linearity or efficiency of the power amplifier.
14. The power amplification system of claim 1 further comprising one or more switches configured to pass or block the biasing signal to a respective one or more of the plurality of cascode amplifiers.
15. The power amplification system of claim 14 further comprising a controller configured to set a respective state of the one or more switches based on a power output.
16. A radio-frequency (RF) module comprising:
a packaging substrate configured to receive a plurality of components; and
a power amplification system implemented on the packaging substrate, the power amplification system including a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal, the power amplifier including a plurality of cascode amplifiers coupled in parallel, and a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal.
17. The RF module of claim 16 wherein the power amplifier includes a cascode power amplifier including a first transistor and a second transistor, the first transistor being biased by the biasing signal, the second transistor being biased by a supplemental biasing signal.
18. The RF module of claim 16 further comprising a supply component implemented on the packaging substrate, the supply component configured to generate an envelope-based supply voltage for powering the power amplifier.
19. A wireless device comprising:
a transceiver configured to generate a radio-frequency (RF) signal;
a front-end module (FEM) in communication with the transceiver, the FEM including a packaging substrate configured to receive a plurality of components, the FEM further including a power amplification system implemented on the packaging substrate, the power amplification system including a power amplifier configured to amplify an input radio-frequency (RF) signal to generate an output RF signal when biased by a biasing signal, the power amplifier including a plurality of cascode amplifiers coupled in parallel, and a bias component configured to generate the biasing signal based on an envelope signal indicative of an envelope of the input RF signal; and
an antenna in communication with the FEM, the antenna configured to transmit the output RF signal received from the power amplification system.