Control node for multi-core system
A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.
1. A computing system comprising:
a plurality of nodes, wherein at least one of the plurality nodes includes an execution unit configured to execute an operation;
an interconnection network coupled to the plurality of nodes, the interconnection network configured to provide interconnections among the plurality of nodes a control node coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes, wherein the operation is part of a task created by the control node.
2. The system of claim 1 , wherein the task includes a task definition designating system resources including at least one of memory, control register, input and output buffers and input and output ports.
3. The system of claim 2 , wherein the control node is operable for starting and stopping the task for the nodes, and wherein the control node assigns a state including suspend, idle, ready or run to the task.
4. The system of claim 3 , wherein the control node can peek to read values in a control register or poke to write values in the control register when the task is stopped.
5. The system of claim 1 , wherein the control node is operable for monitoring the status of nodes.
6. The system of claim 1 , further comprising a memory, and wherein the control node controls memory mapping of the memory.
7. The system of claim 1 , wherein the control node is external to the plurality of nodes.
8. The system of claim 1 , wherein the control node is one of the plurality of nodes.
9. The system of claim 1 , wherein the control node is a RISC processor.
10. The system of claim 2 , wherein the control register includes a go bit, wherein the control node sets the go bit to move the task from the suspend state to the idle state.
11. The system of claim 2 , wherein the control register is in a first node of the plurality of nodes, and the control node is operable to peek and poke into a second control register in a second node of the plurality of nodes.
12. The system of claim 2 , wherein the control node includes a ready to run queue for execution of the task.
13. The system of claim 1 , wherein the control node is operative to assign code to be executed on one of the plurality of nodes, and wherein the control node is an assigning node for execution of a task on one of the plurality of nodes.
14. The system of claim 2 , wherein the task includes a module parameter list stored in the memory.
15. The system of claim 14 , wherein the module parameter list includes a pointer to the node executing the operation.
16. The system of claim 14 , wherein the module parameter list includes a buffer for read data and a buffer for write data.
17. The system of claim 1 , wherein the control node is operative to manage flow control for the plurality of nodes.
18. The system of claim 17 , wherein managing flow control includes setting up ports for either input or output in at least one of the plurality of nodes.
19. The system of claim 17 , wherein managing flow control includes setting up ports on at least one of the plurality of nodes to transmit data from port to port.
20. The system of claim 1 , further comprising a memory, and wherein the control node assigns buffer size and location in the memory.
21. The system of claim 2 , wherein the control node assigns an input buffer to the task, the control node including a count associated with the input buffer.
22. The system of claim 21 , wherein the task is a consumer task or a producer task with an associated consumer or producer count with the buffer.
23. The system of claim 1 , wherein the control node writes to a node control register of one of the plurality of nodes.
24. The system of claim 23 , wherein the node control register includes a bit setting for diagnostics for write/read/check.
25. The system of claim 23 , wherein the node control register includes a setting for initializing a queue of tasks waiting for execution, a queue of incoming data or a queue of outgoing data.
26. The system of claim 1 , wherein each of the plurality of nodes includes a node status register.
27. The system of claim 26 , wherein the control node is operable to set up a translation table to translate a port of the task to an address.
28. A computing system comprising:
a plurality of computing nodes, wherein at least one of the plurality of computing nodes include a control register;
an interconnection network coupled to each of the plurality of computing nodes; and
a control node coupled to the plurality of computing nodes, wherein the control node is operable to store a go-bit in the control register of the at least one node that allows the control node to initiate the operation of a task by the node, wherein the task is created by the control node.
29. The computing system of claim 28 , wherein the control node is operable to place the at least one node in a suspend state by creating a task in the node.
30. The computing system of claim 29 , wherein the control node is operable to assign an idle state to the task when the go-bit is stored.
31. The computing system of claim 28 , wherein the control node is operable to issue an abort command to the node and clear the go-bit in the control register to abandon the task.
32. The computing system of claim 28 , wherein the task includes a consumer count indicating a status of an input buffer associated with the task.
33. The computing system of claim 28 , wherein the task includes a producer count indicating a status of an output buffer associated with the task.
34. The computing system of claim 28 wherein the control node is operative to manage flow control for the plurality of nodes.
35. The computing system of claim 34 , wherein managing flow control includes setting up ports for either input or output in at least one of the plurality of nodes.
36. The computing system of claim 34 , wherein managing flow control includes setting up ports on at least one of the plurality of nodes to transmit data from port to port.
37. A computing system comprising:
a plurality of nodes, each operable to execute an operation;
an interconnection network coupled to the plurality of interconnected nodes; and
control node coupled to the plurality of interconnected nodes, the control node writing to a node control register for enabling operations in at least one of the nodes, wherein the operations are part of a task created by the control node.
38. The computing system of claim 37 , wherein the node control register includes an enable bit, wherein the control node is operable to clear the enable bit to cause at least one of the plurality of nodes to cease operation.
39. The computing system of claim 37 , wherein the node control register includes an abort bit, wherein the control node is operable to set the abort bit to halt execution of the operation.
40. The computing system of claim 37 , wherein the node control register includes a diagnostics bit, wherein the control node is operable to set the diagnostics bit to perform a write/read/check diagnostic.
41. The computing system of claim 37 , wherein the node control register controls queue initialization of a queue of tasks waiting for execution, a queue of incoming data or a queue of outgoing data.
42. A computing system comprising:
a first plurality of nodes, each having a fixed set of input and output buffers, a parameter memory, and operable to execute an operation;
a second plurality of nodes, each having a fixed set of input and output buffers different from those of the first plurality of nodes, and a parameter memory, the second plurality of nodes operable to execute a different operation than the operation of the first plurality of nodes;
a control node coupled to the first and second plurality of nodes, wherein the operations are part of a task created by the control node; and
an interconnection network coupled to the first and second plurality of nodes.
43. A computing system comprising:
a first array of configured nodes, each having a fixed set of input and output buffers, a parameter memory, and operable to execute an operation;
a second array of configured nodes, at least one of the second array of configured nodes having a fixed set of input and output buffers different from those of the first array of nodes, and a parameter memory;
a control node coupled to the first and second array of nodes, wherein the operations are part of a task created by the control node; and
an interconnection network coupled to the first and second array of nodes, the interconnection network operable to configure the first array of nodes and reconfigure the second array of nodes.
44. A computing system comprising:
a plurality of nodes, wherein at least one of the plurality nodes includes an execution unit configured to execute an operation;
an interconnection network coupled to the plurality of nodes, the interconnection network configured to provide interconnections among the plurality of nodes
a control node coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes, wherein the operation is part of a task created by the control node, and wherein the task includes a task definition designating system resources including at least one of memory, control register, input and output buffers and input and output ports, wherein the control node is operable for starting and stopping the task for the nodes, and wherein the control node assigns a state including suspend, idle, ready or run to the task.