Method for interface initialization using bus turn-around
An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.
1. A method for initializing an interface, comprising:
driving a low voltage signal on data lanes and clock lanes;
performing a reset sequence and an initialization of a link configuration register;
driving a high voltage signal to the clock lanes and the data lanes;
driving a bus turn-around (BTA) sequence on the data lanes; and
detecting that the BTA is acknowledged by a host controller.
2. The method of claim 1 , further comprising driving, via the host controller, a high voltage signal on the clock lanes in response to detecting that the BTA is acknowledged by the host controller.
3. The method of claim 1 , wherein driving the low voltage signal is performed by a peripheral device in response to a reset.
4. The method of claim 1 , further comprising starting the initialization after a core power is detected.
5. The method of claim 1 , wherein the BTA is continuously driven until the BTA is acknowledge by the host controller.
6. A method for initializing an interface, comprising:
receiving high voltage signals at a host device from a peripheral device;
accepting bus turn-around requests on a data lane at the host device in response to receiving the high voltage signals for a time exceeding a threshold time;
acknowledging the bus turn-around requests to complete an initialization; and
driving, via the host device, a second set of high voltage signals on the data lane.
7. The method of claim 6 , further comprising sending configuration commands to the peripheral device.
8. The method of claim 6 , further comprising defaulting to a disabled turn-around for the data lane in response to a reset.
9. The method of claim 6 , further comprising enabling a physical layer (PHY) and forcing the data lane into a receiver mode in response to completing the initialization.
10. The method of claim 6 , further comprising sending a set rate packet to the peripheral device to program a high-speed clock frequency for high-speed operation.
11. A device interface, comprising:
a device power lane to receive a high voltage signal from a peripheral device to begin an initialization; and
a data lane to:
receive a bus turn-around request from the peripheral device and send the bus-turn around request to a host device;
receive a bus turn-around acknowledgement from the host device and send the bus turn-around acknowledgment to the peripheral device; and
receive data from the host device.
12. The device interface of claim 11 , wherein the device interface comprises a bidirectional high-bandwidth serial user interface.
13. The device interface of claim 11 , wherein the device interface comprises a duplex high-bandwidth serial user interface.
14. The device interface of claim 11 , further comprising a power on reset lane to be used to reset the user interface in response to receiving a reset voltage.
15. The device interface of claim 11 , further comprising a host power lane to receive power in response to sending the bus turn-around request.
16. The device interface of claim 11 , wherein the device interface is to use ultra-low power states on the data lane for sending control information between data transfers.
17. The device interface of claim 11 , wherein the bus turn-around acknowledgement indicates the completion of the initialization.
18. The device interface of claim 11 , wherein the data lane is to further receive a set rate packet from the host device and send the set rate packet to the peripheral device to program a high-speed clock frequency for high-speed operation.
19. The device interface of claim 11 , further comprising a clock lane to be monitored for a STOP-11 mode, the user interface to further set a connected bit if the STOP-11 mode is detected at the clock lane for a period exceeding a threshold time and the data lane is detected as turned-around to the host device.
20. The device interface of claim 11 , further comprising receiving configuration commands from the host device in a low power mode and sending the configuration commands to the peripheral device.
21. A system for initializing a device interface, comprising:
a high-bandwidth serial user interface further comprising:
a device power lane to receive a high voltage signal from a peripheral device to begin an initialization; and
a data lane to:
receive a bus turn-around request from the peripheral device and send the bus-turn around request to a host device;
receive a bus turn-around acknowledgement from the host device and send the bus turn-around acknowledgment to the peripheral device; and
receive data from the host device.
22. The system of claim 21 , wherein the peripheral device comprises a touch screen display.
23. The system of claim 21 , wherein the peripheral device comprises a camera.
24. The system of claim 21 , wherein the high-bandwidth serial user interface comprises a duplex interface.
25. The system of claim 21 , wherein the high-bandwidth serial user interface comprises a bidirectional interface.