Multi-via redistribution layer for integrated circuits having solder balls
A wafer-level chip-scale package (WLCSP) includes an integrated circuit (IC) chip, and die bonding pads with a redistribution layer (RDL) having multiple via structures located directly below the footprint of a solder ball placed on the bonding pad. The via structures electrically connect the solder ball to a top metal layer of the IC chip. The RDL may extend beyond the solder ball's footprint and have additional vias that connect to the top metal layer, including vias located under and connected to other solder balls. The bonding pads have a low R-on resistance and are not susceptible to thermal-induced cracking.
1. An article of manufacture comprising an integrated circuit (IC), the IC comprising:
a top metal conducting layer;
a passivation layer on top of the top metal conducting layer, wherein the passivation layer comprises openings to the top conducting layer;
a redistribution layer on top of the passivation layer, wherein material of the redistribution layer fills the openings in the passivation layer to form via structures electrically connecting the redistribution layer to the top metal conducting layer; and
a solder ball placed on top of the redistribution layer that has a footprint that spans a first plurality of the via structures of the redistribution layer such that electricity can flow vertically between the solder ball and the top metal conducting layer through the redistribution layer and the first plurality of the via structures,
wherein there is no under-bump metallization (UBM) layer under the solder ball other than the redistribution layer, and
wherein the solder ball is in direct contact with the redistribution layer, and the footprint of the solder ball is vertically aligned with the first plurality of the via structures over the top metal conducting layer.
2. The article of claim 1 , wherein a second plurality of the via structures of the redistribution layer are located outside of the footprint of the solder ball such that electricity can also flow vertically and horizontally between the solder ball and the top conducting layer through the redistribution layer and the second plurality of the via structures.
3. The article of claim 1 , wherein there is no dielectric layer between the passivation layer and the redistribution layer.
4. The article of claim 1 , wherein there is no dielectric layer between the passivation layer and the redistribution layer.
5. The article of claim 1 , wherein there is no dielectric layer between the redistribution layer and the solder ball.
6. The article of claim 1 , wherein the first plurality comprise more than 40 via structures.
7. The article of claim 1 , wherein the article is a wafer-level chip-scale package (WLCSP).
8. The article of claim 3 , wherein there is no dielectric layer between the redistribution layer and the solder ball.
9. The article of claim 6 , wherein the first plurality comprise more than 60 via structures.
10. The article of claim 9 , wherein the first plurality comprise more than 80 via structures.
11. An article of manufacture comprising an integrated circuit (IC), the IC comprising:
a top metal conducting layer;
a passivation layer on top of the top conducting layer, wherein the passivation layer comprises openings to the top conducting layer;
a redistribution layer on top of the passivation layer, wherein material of the redistribution layer fills the openings in the passivation layer to form via structures electrically connecting the redistribution layer to the top conducting layer; and
a solder ball placed on top of the redistribution layer that has a footprint that spans a first plurality of the via structures of the redistribution layer such that electricity can flow vertically between the solder ball and the top conducting layer through the redistribution layer and the first plurality of the via structures, and
wherein the redistribution layer electrically connects the solder ball to at least one other solder ball.
12. The article of claim 11 , wherein a footprint of the at least one other solder ball spans a second plurality of the via structures of the redistribution layer such that electricity can also flow vertically between the at least one other solder ball and the top conducting layer through the redistribution layer and the second plurality of the via structures.
13. The article of claim 12 , wherein a third plurality of the via structures of the redistribution layer extend beyond the footprints of the solder ball and the at least one other solder ball such that electricity can also flow horizontally and vertically between at least one of the solder balls and the top conducting layer through the redistribution layer and the third plurality of the via structures.
14. A method for manufacturing a bonding pad of an integrated circuit (IC) having a top metal conducting layer, the method comprising:
applying a redistribution layer on top of an IC sub-assembly having a passivation layer on top of the top metal conducting layer, wherein:
the passivation layer comprises openings to the top metal conducting layer; and
material of the redistribution layer fills the openings in the passivation layer to form via structures electrically connecting the redistribution layer to the top metal conducting layer;
applying a first solder ball on top of the redistribution layer, wherein a footprint of the first solder ball spans a first plurality of the via structures of the redistribution layer such that electricity can flow vertically between the first solder ball and the top metal conducting layer through the redistribution layer and the first plurality of the via structures; and
applying a second solder ball on top of the redistribution layer, wherein the redistribution layer electrically connects the first solder ball to the second solder ball.
15. The method of claim 14 , wherein a footprint of the second solder ball spans a second plurality of the via structures of the redistribution layer such that electricity can flow vertically between the second solder ball and the top conducting layer through the redistribution layer and the second plurality of the via structures.
16. The method of claim 15 , wherein a third plurality of the via structures of the redistribution layer extend beyond the footprints of the first and second solder balls, such that electricity can flow horizontally and vertically between at least one of the first and second solder balls and the top conducting layer through the redistribution layer and the third plurality of the via structures.