IP Library Granted Patent US 10,192,977
Granted Patent B2
US 10,192,977 · App. 15/122,261 · Granted Jan 29, 2019

Power semiconductor device

Inventors: Akihiko Furukawa (Chiyoda-ku, JP); Shoichi Orita (Chiyoda-ku, JP); Hiroki Muraoka (Chiyoda-ku, JP); Atsushi Narazaki (Chiyoda-ku, JP); Tsuyoshi Kawakami (Chiyoda-ku, JP); Yuji Murakami (Chiyoda-ku, JP)
Assignee: MITSUBISHI ELECTRIC CORPORATION
H01L29/7397H01L29/0619H01L29/0696H01L29/0804H01L29/0821H01L29/1004H01L29/1095H01L29/407H01L29/66348
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,192,977
App. No.
15/122,261
Granted
Jan 29, 2019
Kind
B2
Abstract

In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.

Claims (33)

1. A power semiconductor device controlling a current between an emitter electrode and a collector electrode with a voltage applied to a gate electrode, the device comprising:

a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface;

a second-conductive-type second base region disposed on the first principal surface of the first base region;

at least three groove parts parallel to each other disposed from a surface of the second base region through the second base region to the first base region, the groove parts including a first groove part and a third groove part arranged with a second groove part interposed therebetween;

insulating films covering inner walls of the respective groove parts;

conductive trench gates filled on the insulating films;

a first-conductive-type emitter region disposed in the second base region between the first groove part and the second groove part to be in contact with the first groove part, the first-conductive-type emitter region being electrically connected to the emitter electrode; and

a second-conductive-type collector region disposed on the second principal surface of the first base region,

wherein the first-conductive-type emitter region is not formed in the second base region between the second groove part and the third groove part,

the third groove part does not have a first-conductive-type emitter region in contact therewith,

wherein the trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and

wherein the trench gate embedded in the second groove part is electrically connected to the emitter electrode.

2. The semiconductor device according to claim 1 , wherein at least one or more second groove parts are disposed on each of both sides of the third groove part, and wherein the first groove part is disposed on each side opposite to the third groove part across the second groove parts.

3. The semiconductor device according to claim 1 , wherein two third groove parts are adjacently disposed, wherein one or more second groove parts are disposed on each side such that the two third groove parts are interposed therebetween, wherein the first-conductive-type emitter region is not formed in the second base region between the two third groove parts, and wherein the first groove part is disposed on each side opposite to the third groove parts across the second groove parts.

4. The semiconductor device according to claim 3 , wherein a second-conductive-type contact region electrically connected to the emitter electrode is disposed in the second base region interposed between the two third groove parts.

5. The semiconductor device according to claim 1 , wherein the emitter layers and second-conductive-type contact regions are alternately disposed in the second base region interposed between the first groove part and the second groove part in a direction along a longitudinal direction of the first groove part.

6. A power semiconductor device controlling a current between an emitter electrode and a collector electrode with a voltage applied to a gate electrode, the device comprising:

a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface;

a second-conductive-type second base region disposed in a certain region of the first principal surface of the first base region;

at least three groove parts parallel to each other disposed in the first base region, the groove parts including a first groove part and a third groove part arranged with a second groove part interposed therebetween;

insulating films covering inner walls of the respective groove parts; and

conductive trench gates filled on the insulating films,

wherein the first groove part or the first and second groove parts is disposed from a surface of the second base region through the second base region to the first base region, and

wherein the third groove part is disposed in the first base region,

the semiconductor device further comprising:

a first-conductive-type emitter region disposed in the second base region between the first groove part and the second groove part to be in contact with the first groove part, the first-conductive-type emitter region being electrically connected to the emitter electrode; and

a second-conductive-type collector region disposed on the second principal surface of the first base region,

wherein the trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode,

the third groove part does not have a first-conductive-type emitter region in contact therewith,

wherein the trench gate embedded in the second groove part is electrically connected to the emitter electrode.

7. The semiconductor device according to claim 6 , wherein at least one or more second groove parts are disposed on each of both sides of the third groove part, and wherein the first groove part is disposed on each side opposite to the third groove part across the second groove parts.

8. The semiconductor device according to claim 6 , wherein two third groove parts are adjacently disposed, wherein one or more second groove parts are disposed on each side such that the two third groove parts are interposed therein, and wherein the first groove part is disposed on each side opposite to the third groove parts across the second groove parts.

9. The semiconductor device according to claim 6 , wherein the emitter layers and second-conductive-type contact regions are alternately disposed in the second base region interposed between the first groove part and the second groove part in a direction along a longitudinal direction of the first groove part.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2016
From: FURUKAWA, AKIHIKO; ORITA, SHOICHI; MURAOKA, HIROKI; NARAZAKI, ATSUSHI; KAWAKAMI, TSUYOSHI; MURAKAMI, YUJI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 039564/0671 →
Priority Claims (1)
JP 2014-087462 · Apr 21, 2014 · national
Continuity (1)
Related Publication 20160372585A1 · Dec 22, 2016
Cited By (1)
US 12,588,263