Insulated gate bipolar transistor (IGBT) semiconductor device with reduced turn-on loss
A semiconductor device includes first and second electrodes, a semiconductor part, a structure body, and an insulating part. The semiconductor part includes first to fifth semiconductor regions. The structure body includes a gate part and a dummy part. The gate part includes at least one gate electrode. The dummy part includes at least two dummy electrodes. The gate part and the dummy part are alternately arranged. The insulating part is located between the gate electrode and the semiconductor part. The gate part is located in the fourth semiconductor region. A first potential is applied to the second electrode. A second potential that is greater than the first potential is applied to the gate electrode. A third potential that is greater than the first potential is applied to the dummy electrode located at a position next to the gate part.
1 . A semiconductor device, comprising:
a first electrode;
a semiconductor part including:
a first semiconductor region located on the first electrode, the first semiconductor region being of a p-type,
a second semiconductor region located on the first semiconductor region, the second semiconductor region being of an n-type,
a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the p-type,
a fourth semiconductor region located on the third semiconductor region, the fourth semiconductor region being of the n-type, and
a fifth semiconductor region located on the third semiconductor region, the fifth semiconductor region being of the p-type;
a second electrode located on the semiconductor part;
a structure body including a gate part and a dummy part alternately arranged in a second direction perpendicular to a first direction, the gate part including at least one gate electrode, the dummy part including at least two dummy electrodes, the first direction being from the first semiconductor region toward the second semiconductor region; and
an insulating part located between the gate electrode and the semiconductor part, the gate part being located in the fourth semiconductor region, the gate electrode being electrically insulated from the second electrode, the dummy electrode located at a position next to the gate part being electrically insulated from the second electrode, and the dummy electrode being not in contact with the fourth semiconductor region.
2 . The device according to claim 1 , wherein
the fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction, and
the dummy parts are located in the fifth semiconductor region.
3 . The device according to claim 1 , wherein
the second electrode includes:
a first conductive part located on the semiconductor part; and
a second conductive part located under the first conductive part, the second conductive part being positioned between two of the gate electrodes that are next to each other in the second direction, and
the third semiconductor region includes:
a first part; and
a second part located on the first part, the fourth semiconductor region is located on the first part, the fourth semiconductor region and the second part are alternately arranged in the second direction, the fifth semiconductor region is located under the second conductive part, and the dummy part is located in the second part.
4 . The device according to claim 1 , wherein
the gate part includes three of the gate electrodes, and
the dummy part includes three of the dummy electrodes.
5 . The device according to claim 1 , wherein the dummy electrode that is located at a position next to the gate part is connected to the gate electrode.
6 . The device according to claim 5 , wherein
the fourth semiconductor region and the fifth semiconductor region are alternately arranged in the second direction, and
the dummy part is located in the fifth semiconductor region.
7 . The device according to claim 5 , wherein
the second electrode includes:
a first conductive part located on the semiconductor part; and
a second conductive part located under the first conductive part, the second conductive part being positioned between two of the gate electrodes that are next to each other in the second direction, and
the third semiconductor region includes:
a first part; and
a second part located on the first part, the fourth semiconductor region is located on the first part, the fourth semiconductor region and the second part are alternately arranged in the second direction, the fifth semiconductor region is located under the second conductive part, and the dummy part is located in the second part.
8 . The device according to claim 5 , wherein
the dummy part includes at least three of the dummy electrodes, and
the dummy electrode that is located at a position not next to the gate part is connected to the second electrode.
9 . The device according to claim 5 , wherein
the gate part includes three of the gate electrodes, and
the dummy part includes three of the dummy electrodes.
10 . The device according to claim 1 , wherein a first potential is applied to the second electrode, a second potential is applied to the gate electrode, the second potential is greater than the first potential, a third potential is applied to the dummy electrode located at a position next to the gate part, and the third potential is greater than the first potential.
11 . The device according to claim 10 , wherein the second potential is 15 V.
12 . The device according to claim 10 , wherein the third potential is equal to the second potential.
13 . The device according to claim 10 , wherein the third potential is equal to the second potential.
14 . The device according to claim 10 , wherein the dummy part includes at least three of the dummy electrodes, and the first potential is applied to the dummy electrode located at a position not next to the gate part.
15 . A semiconductor device, comprising:
a first electrode;
a semiconductor part including:
a first semiconductor region located on the first electrode, the first semiconductor region being of a p-type,
a second semiconductor region located on the first semiconductor region, the second semiconductor region being of an n-type,
a third semiconductor region located on the second semiconductor region, the third semiconductor region being of the p-type,
a fourth semiconductor region located on the third semiconductor region, the fourth semiconductor region being of the n-type, and
a fifth semiconductor region located on the third semiconductor region, the fifth semiconductor region being of the p-type;
a second electrode located on the semiconductor part;
a structure body including a gate part and a dummy part alternately arranged in a second direction perpendicular to a first direction, the gate part including at least one gate electrode, the dummy part including a first dummy electrode and a second dummy electrode, the first direction being from the first semiconductor region toward the second semiconductor region; and
an insulating part located between the gate electrode and the semiconductor part, the gate part being located in the fourth semiconductor region, the first dummy electrode being located between the gate part and the second dummy electrode, the first dummy electrode being adjacent to the second dummy electrode without the fourth semiconductor region between the first dummy electrode and the second dummy electrode, the gate electrode being electrically insulated from the second electrode, the first dummy electrode being electrically insulated from the second electrode, the first dummy electrode being electrically insulated from the second dummy electrode.
16 . The device according to claim 15 , wherein the second electrode includes:
a first conductive part located on the semiconductor part; and
a second conductive part located under the first conductive part, the second conductive part being positioned between two of the gate electrodes that are next to each other in the second direction, the third semiconductor region includes:
a first part; and
a second part located on the first part, the fourth semiconductor region is located on the first part, the fourth semiconductor region and the second part are alternately arranged in the second direction, the fifth semiconductor region is located under the second conductive part, and the dummy part is located in the second part.
17 . The device according to claim 15 , wherein the first dummy electrode is electrically connected to the gate electrode.