Semiconductor device
Plural gate trenches are formed on an upper surface side of a semiconductor substrate of a first conductivity type. Gate electrodes are embedded in the plural gate trenches. Plural dummy gate trenches are formed at equivalent intervals between the neighboring gate trenches on the upper surface side of the semiconductor substrate. Dummy gate electrodes are embedded in the plural dummy gate trenches and connected with an emitter electrode. An interval between the gate trench and the dummy gate trench that neighbor each other is shorter than an interval between the neighboring dummy gate trenches.
1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
plural gate trenches formed on an upper surface side of the semiconductor substrate;
gate electrodes embedded in the plural gate trenches;
a gate insulation film formed between the gate electrodes and the semiconductor substrate;
a channel layer of a second conductivity type formed in a surface layer portion on the upper surface side of the semiconductor substrate;
a contact layer of the second conductivity type having a higher impurity peak concentration than the channel layer and formed in a surface layer portion of the channel layer;
an emitter layer of the first conductivity type formed in the surface layer portion of the channel layer so as to abut the gate trench;
an emitter electrode connected with the contact layer;
plural dummy gate trenches formed at equivalent intervals between the neighboring gate trenches on the upper surface side of the semiconductor substrate;
dummy gate electrodes embedded in the plural dummy gate trenches and connected with the emitter electrode; and
a dummy gate insulation film formed between the dummy gate electrodes and the semiconductor substrate,
wherein an interval between the gate trench and the dummy gate trench that neighbor each other is shorter than an interval between the neighboring dummy gate trenches.
2. The semiconductor device according to claim 1 , wherein the interval between the neighboring dummy gate trenches is T 2 , a half value of a width of the gate trench is r t1 , a half value of a width of the dummy gate trench is r t2 , an impurity concentration of the semiconductor substrate in a bottom of the gate trench is N 1 , an impurity concentration of the semiconductor substrate in a bottom of the dummy gate trench is N 2 ,
a distance r 1 from the bottom of the gate trench to an end of the depletion layer and a distance r 2 from the bottom of the dummy gate trench to the end of the depletion layer satisfy
2
r
2
=
T
2
(
r
1
2
-
r
t
1
2
2
)
+
r
1
2
ln
(
r
1
r
t
1
)
(
r
2
2
-
r
t
2
2
2
)
+
r
2
2
ln
(
r
2
r
t
2
)
=
N
2
N
1
,
D is a total number of the gate trenches and the dummy gate trenches included in a unit cell of the semiconductor device, W is a width of the unit cell, d is a difference between depths of the dummy gate trench and the gate trench, r′=r 2 −r 1 , and
an interval T 1 between the gate trench and the dummy gate trench that neighbor each other satisfies
D
·
(
D
-
4
)
·
T
1
2
+
4
[
W
-
(
D
-
2
)
·
r
′
]
·
T
1
+
(
D
-
2
)
2
·
d
2
-
2
W
2
+
[
(
D
-
2
)
·
r
′
+
W
]
2
≦
0
T
1
≥
W
2
·
(
D
-
1
)
.
3. The semiconductor device according to claim 2 , wherein a width of the gate trench is narrower than a width of the dummy gate trench.
4. The semiconductor device according to claim 3 , further comprising an N type carrier accumulation layer formed between the semiconductor substrate and the channel layer,
wherein the interval between the neighboring dummy gate trenches is shorter than 15 μm.
5. The semiconductor device according to claim 4 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
6. The semiconductor device according to claim 3 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
7. The semiconductor device according to claim 2 , further comprising an N type carrier accumulation layer formed between the semiconductor substrate and the channel layer,
wherein the interval between the neighboring dummy gate trenches is shorter than 15 μm.
8. The semiconductor device according to claim 7 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
9. The semiconductor device according to claim 2 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
10. The semiconductor device according to claim 1 , wherein a width of the gate trench is narrower than a width of the dummy gate trench.
11. The semiconductor device according to claim 10 , further comprising an N type carrier accumulation layer formed between the semiconductor substrate and the channel layer,
wherein the interval between the neighboring dummy gate trenches is shorter than 15 μm.
12. The semiconductor device according to claim 11 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
13. The semiconductor device according to claim 10 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
14. The semiconductor device according to claim 1 , further comprising an N type carrier accumulation layer formed between the semiconductor substrate and the channel layer,
wherein the interval between the neighboring dummy gate trenches is shorter than 15 μm.
15. The semiconductor device according to claim 14 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.
16. The semiconductor device according to claim 1 , wherein the semiconductor substrate is formed of a wide-band-gap semiconductor.